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    Bipolar transistor structure with base protruding from emitter/collector and methods to form same
    12.
    发明授权
    Bipolar transistor structure with base protruding from emitter/collector and methods to form same 有权

    公开(公告)号：US11961901B2

    公开(公告)日：2024-04-16

    申请号：US17659357

    申请日：2022-04-15

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Shesh Mani Pandey

    IPC: H01L29/735 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

    CPC classification number: H01L29/735 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/6625

    Abstract: The disclosure provides a bipolar transistor structure with multiple bases, and related methods. A bipolar transistor structure includes a first emitter/collector (E/C) material above an insulator. The first E/C material has first sidewall and a second sidewall over the insulator. A first base is above the insulator adjacent the first sidewall of the first E/C material. A second base is above the insulator adjacent the second sidewall of the first E/C material. A second E/C material is above the insulator and adjacent the first base. A width of the first base between the first E/C material and the second E/C material is less than a width of the first E/C material, and the first base protrudes horizontally outward from an end of the first E/C material and an end of the second E/C material.

    BIPOLAR TRANSISTOR STRUCTURE WITH BASE PROTRUDING FROM EMITTER/COLLECTOR AND METHODS TO FORM SAME
    15.
    发明公开
    BIPOLAR TRANSISTOR STRUCTURE WITH BASE PROTRUDING FROM EMITTER/COLLECTOR AND METHODS TO FORM SAME 审中-公开

    公开(公告)号：US20230178637A1

    公开(公告)日：2023-06-08

    申请号：US17659357

    申请日：2022-04-15

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Shesh Mani Pandey

    IPC: H01L29/735 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

    CPC classification number: H01L29/735 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/6625

    Abstract: The disclosure provides a bipolar transistor structure with multiple bases, and related methods. A bipolar transistor structure includes a first emitter/collector (E/C) material above an insulator. The first E/C material has first sidewall and a second sidewall over the insulator. A first base is above the insulator adjacent the first sidewall of the first E/C material. A second base is above the insulator adjacent the second sidewall of the first E/C material. A second E/C material is above the insulator and adjacent the first base. A width of the first base between the first E/C material and the second E/C material is less than a width of the first E/C material, and the first base protrudes horizontally outward from an end of the first E/C material and an end of the second E/C material.

    Split gate (SG) memory device and novel methods of making the SG-memory device
    16.
    发明授权
    Split gate (SG) memory device and novel methods of making the SG-memory device 有权

    公开(公告)号：US11450678B2

    公开(公告)日：2022-09-20

    申请号：US16683439

    申请日：2019-11-14

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Hui Zang ,  Ruilong Xie ,  Shesh Mani Pandey

    IPC: H01L29/423 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/51

    Abstract: One illustrative integrated circuit (IC) product disclosed herein includes a selection gate electrode and a first gate insulation layer positioned above a substrate and a memory gate electrode positioned above the substrate and adjacent the selection gate electrode, wherein the memory gate electrode comprises a bottom surface and first and second opposing sidewall surfaces. This embodiment of the IC product also includes a plurality of layers of insulating material, wherein a first portion of the layers of insulating material is positioned between the first gate insulation layer and the first opposing sidewall of the memory gate electrode, a second portion of the layers of insulating material is positioned between the bottom surface of the memory gate electrode and the upper surface of the semiconductor substrate, and a third portion of the layers of insulating material is positioned on the second opposing sidewall of the conductive memory gate electrode.

    MULTI-LEVEL ISOLATION STRUCTURE
    17.
    发明申请
    MULTI-LEVEL ISOLATION STRUCTURE 有权

    公开(公告)号：US20210313321A1

    公开(公告)日：2021-10-07

    申请号：US16842075

    申请日：2020-04-07

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Haiting Wang ,  Sipeng Gu ,  Shesh Mani Pandey ,  Lixia Lei ,  Gregory Costrini

    IPC: H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L27/092 ,  H01L21/8234

    Abstract: One illustrative device disclosed herein includes at least one fin structure and an isolation structure comprising a stepped upper surface comprising a first region and a second region. The first region has a first upper surface and the second region has a second upper surface, wherein the first upper surface is positioned at a first level and the second upper surface is positioned at a second level and wherein the first level is below the second level. In this illustrative example, the device also includes a gate structure comprising a first portion and a second portion, wherein the first portion of the gate structure is positioned above the first upper surface of the isolation structure and above the at least one fin structure and wherein the second portion of the gate structure is positioned above the second upper surface of the isolation structure.

    Silicon-controlled rectifiers in a silicon-on-insulator technology
    19.
    发明授权
    Silicon-controlled rectifiers in a silicon-on-insulator technology 有权

    公开(公告)号：US11935946B2

    公开(公告)日：2024-03-19

    申请号：US17849867

    申请日：2022-06-27

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Shesh Mani Pandey ,  Souvick Mitra ,  Anindya Nath

    IPC: H01L29/745 ,  H01L29/66

    CPC classification number: H01L29/7455 ,  H01L29/66363

    Abstract: Structures for a silicon-controlled rectifier and methods of forming a structure for a silicon-controlled rectifier. The structure comprises a semiconductor substrate, a dielectric layer on the semiconductor substrate, and a first well and a second well in the semiconductor substrate beneath the dielectric layer. The first well has a first conductivity type, the second well has a second conductivity type opposite to the first conductivity type, and the second well adjoins the first well along a p-n junction. The structure further comprises a first terminal and a second terminal above the dielectric layer, a first connection extending through the dielectric layer from the first terminal to the first well, and a second connection extending through the dielectric layer from the second terminal to the second well.

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