公开(公告)号：US20060021795A1

公开(公告)日：2006-02-02

申请号：US10910506

申请日：2004-08-02

Applicant: Gregory Howard ,  Navin Kalidas ,  Paul Hundt ,  Gary Morrison

Inventor： Gregory Howard ,  Navin Kalidas ,  Paul Hundt ,  Gary Morrison

IPC: H01R12/04

CPC classification number: H05K3/3426 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H05K2201/10303 ,  H05K2201/10704 ,  H05K2201/10984 ,  Y02P70/613 ,  Y10T29/49147 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Semiconductor chip (1101) of a ball grid array device (1100) is mounted onto tape substrate (1102) using attach adhesive (1103). The metal layer on the top surface of substrate (1102) uses between about 30% to 90% of its area for connecting lines (1104), and only the remainder for members/rings (1105) and terminals (1106). Routing of differential pair signals and large numbers of signals on a single layer tape package are feasible. This embodiment creates an inexpensive high performance tape ball grid array package for chip-scale devices. Terminals (1106) serve the connection (by bonding wires or reflow bumps) to the chip contact pads. Inserted in members/rings (1105) are the conductive pins (1107), which serve as anchors for the solder bodies/balls (1108). Pins (1107) are substantially insensitive to the thermomechanical stresses, which occur in device (1100) during assembly, testing and operation.

Abstract translation: 使用附着粘合剂（1103）将球栅阵列器件（1100）的半导体芯片（1101）安装到带基片（1102）上。 衬底（1102）的顶表面上的金属层使用其用于连接线（1104）的面积的约30％至90％，而仅用于构件/环（1105）和端子（1106）的剩余部分。 单层磁带封装上的差分对信号和大量信号的路由是可行的。 该实施例为芯片级设备创造了便宜的高性能带状球栅阵列封装。 端子（1106）将连接（通过接合电线或回流焊盘）连接到芯片接触焊盘。 插入在构件/环（1105）中的是用作焊料体/球（1108）的锚定件的导电销（1107）。 引脚（1107）对组装，测试和操作期间在装置（1100）中发生的热机械应力基本上不敏感。

公开(公告)号：US20250083916A1

公开(公告)日：2025-03-13

申请号：US18244286

申请日：2023-09-10

Applicant: Gary Morrison

Inventor： Gary Morrison

IPC: B65H18/02 ,  B65H19/30

Abstract: A reel carrier that includes a pallet having a platform bound by a frame and a shaft. The carrier includes a reel that is supported on the shaft. The reel includes a round drum rotatable about the shaft, wherein the rotation may be in a forward and/or a reverse or backward rotational direction. The carrier also includes a motor operably coupled to cause rotation of the drum and may be further operably coupled to cause deployment and/or retraction of one or more wheels included with the pallet, wherein the motor also controls locomotion of the one or more wheels.

公开(公告)号：US20060179183A1

公开(公告)日：2006-08-10

申请号：US11054372

申请日：2005-02-09

Applicant: Mark Brittain ,  Warren Maule ,  Gary Morrison ,  Jeffrey Stuecheli

Inventor： Mark Brittain ,  Warren Maule ,  Gary Morrison ,  Jeffrey Stuecheli

IPC: G06F13/28

CPC classification number: G06F13/28 ,  G06F13/161 ,  G11C5/04

Abstract: Multiple write buffers are provided within each memory module and are utilized to buffer multiple received write data forwarded to the chip via a write-to-buffer data operation. When a write is received at the memory controller, the memory controller first issues the write-to-buffer (data) operation and the data is forwarded to one of the write buffers. Multiple writes targeting the same DIMM are thus buffered. When all of the available buffers at a memory module are full, the memory controller issues the set of address only write commands to the memory module. The control logic of the DIMM streams all of the buffered write data to the memory device(s) in one continuous burst. By buffering multiple writes and then writing all buffered write data within the DIMM in a single burst, the write-to-read turnaround penalty of the memory module's data bus is substantially minimized.

Abstract translation: 在每个存储器模块内提供多个写入缓冲器，并且用于经由写入缓冲器数据操作来缓冲转发到芯片的多个接收到的写入数据。 当在存储器控制器处接收到写入时，存储器控制器首先发出写入缓冲器（数据）操作，并将数据转发到写入缓冲器之一。 因此，针对同一DIMM的多个写入被缓存。 当内存模块中的所有可用缓冲区都已满时，内存控制器会向内存模块发出一组仅地址写入命令。 DIMM的控制逻辑将所有缓冲的写入数据以一个连续的脉冲串流式传输到存储器件。 通过缓冲多个写入，然后以单个脉冲串将所有缓冲的写入数据写入DIMM内，内存模块的数据总线的写入读取周转损失基本上最小化。

公开(公告)号：US5451947A

公开(公告)日：1995-09-19

申请号：US200613

申请日：1994-02-23

Applicant: Gary Morrison

Inventor： Gary Morrison

IPC: H03M1/48 ,  G01R19/25 ,  G01R21/133 ,  H03M1/20

CPC classification number: G01R19/25 ,  G01R21/133 ,  H03M1/201

Abstract: A system for analogue to digital conversion comprising a means (4) for receiving an input analogue signal, a dither generator for adding a dither signal and an analogue to digital converter (2) for converting the combined input signal and dither signal to a digital value, characterized in that the dither generator provides a dither signal of a form comprising a first periodic dither signal having superimposed and being shaped by a second signal having at least one component which varies the first periodic dither signal over at least one quantization interval of the analogue to digital converter.

Abstract translation: 一种用于模数转换的系统，包括用于接收输入模拟信号的装置（4），用于添加抖动信号的抖动发生器和用于将组合输入信号和抖动信号转换成数字值的模数转换器（2） 其特征在于，所述抖动发生器提供包括第一周期性抖动信号的抖动信号，所述第一周期性抖动信号已被叠加并被第二信号整形，所述第二信号具有至少一个分量，所述至少一个分量通过所述模拟信号的至少一个量化间隔改变第一周期性抖动信号 到数字转换器。