公开(公告)号：US20120070605A1

公开(公告)日：2012-03-22

申请号：US13375287

申请日：2010-09-17

Applicant: Makoto Sasaki ,  Shin Harada ,  Taro Nishiguchi ,  Kyoko Okita ,  Hiroki Inoue ,  Yasuo Namikawa ,  Shinsuke Fujiwara

Inventor： Makoto Sasaki ,  Shin Harada ,  Taro Nishiguchi ,  Kyoko Okita ,  Hiroki Inoue ,  Yasuo Namikawa ,  Shinsuke Fujiwara

IPC: B32B7/04 ,  B28D5/00 ,  C30B23/02 ,  C01B31/36 ,  B32B9/04

CPC classification number: C30B29/36 ,  C30B23/00 ,  H01L21/02002 ,  Y10T428/192

Abstract: An SiC ingot includes a bottom face having 4 sides; four side faces extending from the bottom face in a direction intersecting the direction of the bottom face; and a growth face connected with the side faces located at a side opposite to the bottom face. At least one of the bottom face, the side faces, and the growth face is the {0001} plane, {1-100} plane, {11-20} plane, or a plane having an inclination within 10° relative to these planes.

Abstract translation: SiC锭包括具有4个侧面的底面; 四个侧面从与底面方向相交的方向从底面延伸; 以及与位于与底面相对的一侧的侧面连接的生长面。 底面，侧面和生长面中的至少一个是{0001}面，{1-100}面，{11-20}面，或相对于这些平面倾斜10°以内的平面 。

公开(公告)号：US20120033487A1

公开(公告)日：2012-02-09

申请号：US13195105

申请日：2011-08-01

Applicant: Hiroki Inoue ,  Kiyoshi Kato ,  Takanori Matsuzaki ,  Shuhei Nagatsuka

Inventor： Hiroki Inoue ,  Kiyoshi Kato ,  Takanori Matsuzaki ,  Shuhei Nagatsuka

IPC: G11C11/24 ,  H01L27/108

CPC classification number: H01L27/1052 ,  G11C11/404 ,  G11C11/405 ,  G11C11/4091 ,  G11C16/0408 ,  G11C16/08 ,  G11C16/24 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/425 ,  H01L21/441 ,  H01L21/477 ,  H01L27/108 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/66969 ,  H01L29/78651 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device including a nonvolatile memory cell in which a writing transistor which includes an oxide semiconductor, a reading transistor which includes a semiconductor material different from that of the writing transistor, and a capacitor are included is provided. Data is written to the memory cell by turning on the writing transistor and applying a potential to a node where a source electrode (or a drain electrode) of the writing transistor, one electrode of the capacitor, and a gate electrode of the reading transistor are electrically connected, and then turning off the writing transistor, so that the predetermined amount of charge is held in the node. Further, when a p-channel transistor is used as the reading transistor, a reading potential is a positive potential.

Abstract translation: 提供了包括非易失性存储单元的半导体器件，其中包括包括氧化物半导体的写入晶体管，包括与写入晶体管不同的半导体材料的读取晶体管和电容器。 通过接通写入晶体管并将电位施加到写入晶体管的源极（或电极），电容器的一个电极和读取晶体管的栅电极的节点处，将数据写入存储单元 电连接，然后关闭写入晶体管，使得预定量的电荷被保持在节点中。 此外，当使用p沟道晶体管作为读取晶体管时，读取电位为正电位。

公开(公告)号：US20120033486A1

公开(公告)日：2012-02-09

申请号：US13195089

申请日：2011-08-01

Applicant: Hiroki Inoue ,  Kiyoshi Kato ,  Takanori Matsuzaki ,  Shuhei Nagatsuka

Inventor： Hiroki Inoue ,  Kiyoshi Kato ,  Takanori Matsuzaki ,  Shuhei Nagatsuka

IPC: G11C11/24 ,  H01L27/06 ,  H01L29/04

CPC classification number: G11C16/0408 ,  G11C11/405 ,  G11C16/02

Abstract: It is an object to provide a semiconductor device with a novel structure in which stored data can be held even when power is not supplied, and does not have a limitation on the number of writing operations. A semiconductor device includes a plurality of memory cells each including a transistor including a first semiconductor material, a transistor including a second semiconductor material that is different from the first semiconductor material, and a capacitor, and a potential switching circuit having a function of supplying a power supply potential to a source line in a writing period. Thus, power consumption of the semiconductor device can be sufficiently suppressed.

Abstract translation: 本发明的目的是提供一种具有新颖结构的半导体器件，其中即使在未提供电力的情况下也可以保持存储的数据，并且对写入操作的数量没有限制。 半导体器件包括多个存储单元，每个存储单元包括包括第一半导体材料的晶体管，包括与第一半导体材料不同的第二半导体材料的晶体管，以及电容器，以及电位切换电路， 在写作期间的电源供应潜力。 因此，可以充分地抑制半导体器件的功耗。

公开(公告)号：US20120017826A1

公开(公告)日：2012-01-26

申请号：US13258126

申请日：2010-09-28

Applicant: Taro Nishiguchi ,  Makoto Sasaki ,  Shin Harada ,  Kyoko Okita ,  Hiroki Inoue ,  Yasuo Namikawa

Inventor： Taro Nishiguchi ,  Makoto Sasaki ,  Shin Harada ,  Kyoko Okita ,  Hiroki Inoue ,  Yasuo Namikawa

IPC: C30B23/06

CPC classification number: C30B29/36 ,  C30B23/025 ,  C30B33/06 ,  H01L21/02002 ,  H01L21/02378 ,  H01L21/02529 ,  H01L21/02631 ,  H01L29/1608

Abstract: A supporting portion (30c) made of silicon carbide has irregularities at at least a portion of a main surface (FO). The supporting portion (30c) and at least one single crystal substrate (11) made of silicon carbide are stacked such that the backside surface (B1) of each at least one single crystal substrate (11) and the main surface (FO) of the supporting portion (30c) having irregularities formed contact each other. In order to connect the backside surface (B1) of each at least one single crystal substrate (11) to the supporting portion (30c), the supporting portion (30c) and at least one single crystal substrate (11) are heated such that the temperature of the supporting portion (30c) exceeds the sublimation temperature of silicon carbide, and the temperature of each at least one single crystal substrate (11) is below the temperature of the supporting portion (30c).

Abstract translation: 由碳化硅制成的支撑部分（30c）在主表面（FO）的至少一部分处具有凹凸。 支撑部（30c）和由碳化硅构成的至少一个单晶基板（11）被层叠，使得每个至少一个单晶基板（11）的背面（B1）和主晶面 具有形成彼此接触的凹凸的支撑部（30c）。 为了将每个至少一个单晶衬底（11）的背面（B1）连接到支撑部分（30c），支撑部分（30c）和至少一个单晶衬底（11）被加热，使得 支撑部分（30c）的温度超过碳化硅的升华温度，并且每个至少一个单晶衬底（11）的温度低于支撑部分（30c）的温度。

公开(公告)号：US20110278593A1

公开(公告)日：2011-11-17

申请号：US13104219

申请日：2011-05-10

Applicant: Taro Nishiguchi ,  Makoto Sasaki ,  Shin Harada ,  Kyoko Okita ,  Hiroki Inoue ,  Yasuo Namikawa

Inventor： Taro Nishiguchi ,  Makoto Sasaki ,  Shin Harada ,  Kyoko Okita ,  Hiroki Inoue ,  Yasuo Namikawa

IPC: H01L29/12 ,  C30B23/02 ,  H01L21/20 ,  B32B13/04

CPC classification number: H01L29/7802 ,  C30B23/02 ,  C30B29/36 ,  H01L21/02378 ,  H01L21/02529 ,  H01L21/02631 ,  H01L21/0475 ,  H01L21/2007 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/66068

Abstract: A method for manufacturing a silicon carbide substrate includes the steps of: preparing a SiC substrate made of single-crystal silicon carbide; disposing a base substrate in a crucible so as to face a main surface of the SiC substrate; and forming a base layer made of silicon carbide in contact with the main surface of the SiC substrate, by heating the base substrate in the crucible to fall within a range of temperature higher than a sublimation temperature of silicon carbide constituting the base substrate. In the step of forming the base layer, a gas containing silicon is introduced into the crucible.

Abstract translation: 一种制造碳化硅衬底的方法包括以下步骤：制备由单晶碳化硅制成的SiC衬底; 将基底基板设置在坩埚内以面对SiC基板的主表面; 以及通过加热坩埚中的基底基底而形成与碳化硅基体的主表面接触的碳化硅制成的基底层，使其落入构成基底基板的碳化硅的升华温度以上的温度范围内。 在形成基层的步骤中，将含硅的气体引入坩埚中。

公开(公告)号：US20110199807A1

公开(公告)日：2011-08-18

申请号：US13022292

申请日：2011-02-07

Applicant: Toshihiko Saito ,  Takanori Matsuzaki ,  Shuhei Nagatsuka ,  Hiroki Inoue

Inventor： Toshihiko Saito ,  Takanori Matsuzaki ,  Shuhei Nagatsuka ,  Hiroki Inoue

IPC: G11C5/06 ,  H01L29/12

CPC classification number: G11C11/405 ,  H01L27/11521 ,  H01L27/1156 ,  H01L27/1225 ,  H01L28/40

Abstract: A semiconductor device includes a first signal line, a second signal line, a memory cell, and a potential converter circuit. The memory cell includes a first transistor including a first gate electrode, a first source electrode, a first drain electrode, and a first channel formation region; a second transistor including a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region; and a capacitor. The first channel formation region and the second channel formation region include different semiconductor materials. The second drain electrode, one electrode of the capacitor, and the first gate electrode are electrically connected to one another. The second gate electrode is electrically connected to the potential converter circuit through the second signal line.

Abstract translation: 半导体器件包括第一信号线，第二信号线，存储单元和电位转换器电路。 存储单元包括：第一晶体管，包括第一栅极电极，第一源电极，第一漏极电极和第一沟道形成区域; 第二晶体管，包括第二栅极电极，第二源极电极，第二漏极电极和第二沟道形成区域; 和电容器。 第一沟道形成区域和第二沟道形成区域包括不同的半导体材料。 第二漏电极，电容器的一个电极和第一栅电极彼此电连接。 第二栅极通过第二信号线电连接到电位转换器电路。

公开(公告)号：US07960953B2

公开(公告)日：2011-06-14

申请号：US12096755

申请日：2006-12-06

Applicant: Hiroki Inoue

Inventor： Hiroki Inoue

IPC: G05F1/40 ,  G05F5/00

CPC classification number: G05F1/575

Abstract: A regulator circuit stabilizes the input voltage applied to an input terminal before outputting the output voltage via an output terminal. An output transistor is provided between the input terminal and the output terminal. An error amplifier adjusts the voltage applied to the control terminal of the output transistor such that a voltage that corresponds to the output voltage approaches a predetermined reference voltage. A fluctuation detection capacitor is provided on a path from the input terminal to the grounded terminal. One terminal of the fluctuation detection capacitor is set to a fixed electric potential. In a case that the input voltage is lower than the voltage at the other terminal of the fluctuation detection capacitor, an undershoot suppressing circuit forcibly reduces the gate voltage of the output transistor.

Abstract translation: 在通过输出端子输出输出电压之前，调节器电路稳定施加到输入端子的输入电压。 输入晶体管设置在输入端和输出端之间。 误差放大器调整施加到输出晶体管的控制端子的电压，使得对应于输出电压的电压接近预定的参考电压。 在从输入端子到接地端子的路径上设置有波动检测电容器。 波动检测电容器的一端设定为固定电位。 在输入电压低于波动检测电容器的另一端的电压的情况下，下冲抑制电路强制地降低输出晶体管的栅极电压。

公开(公告)号：US07879779B2

公开(公告)日：2011-02-01

申请号：US10585146

申请日：2005-01-11

Applicant: Kei Watanabe ,  Akira Matsuo ,  Hiroki Inoue

Inventor： Kei Watanabe ,  Akira Matsuo ,  Hiroki Inoue

IPC: A61K7/02

CPC classification number: A61K8/06 ,  A61K8/0295 ,  A61K8/068 ,  A61K8/342 ,  A61K8/361 ,  A61K8/92 ,  A61Q19/10

Abstract: The objective of this invention is to provide an oil-based cleansing composition which retains high performance capability for cleansing, is free from the occurrence of cloudiness in the appearance and does not cause the reduction of the performance capability for massaging, even when water is interfused therein, and further is reduced in the irritation to an eye and is of good safety.An oil-based cleansing composition of this invention is characterized in that comprising (A) a nonionic surfactant having a HLB of 6 to 14, and (B) an oil component, and said oil-based cleansing composition satisfies the following conditions (1) and (2): (1) the amount of water in the composition is less than 5% by mass, and (2) a micellar aqueous solution phase or a bicontinuous microemulsion phase is formed when said oil-based cleansing composition and water are mixed in the ratio of 4:6.

Abstract translation: 本发明的目的是提供一种保持高性能的清洁剂的油性清洁组合物，即使在水混合时也不会引起外观浑浊的发生，并且不会降低按摩的性能能力 并且进一步减少对眼睛的刺激并且具有良好的安全性。 本发明的油性清洁组合物的特征在于：（A）HLB为6〜14的非离子表面活性剂，（B）油性成分，所述油性清洁组合物满足下述条件（1） 和（2）：（1）组合物中的水量小于5质量％，（2）当所述油性清洁组合物和水混合时，形成胶束水溶液相或双连续微乳液相 比例为4：6。

公开(公告)号：US07863881B2

公开(公告)日：2011-01-04

申请号：US12096745

申请日：2006-12-06

Applicant: Hiroki Inoue

Inventor： Hiroki Inoue

IPC: G05F1/40 ,  G05F1/56

CPC classification number: G05F1/575

Abstract: An output transistor is provided between an input terminal and an output terminal. An error amplifier adjusts the gate voltage of the output transistor such that the voltage that corresponds to the output voltage approaches a predetermined reference voltage. A fluctuation detection capacitor is provided on a path from the input terminal to a grounded terminal, which sets one terminal thereof to a fixed voltage. A current feedback circuit supplies, to the gate of the output transistor, the current that corresponds to the current that flows through the fluctuation detection capacitor. A clamp circuit clamps the gate voltage of the output transistor. The clamp circuit 30 clamps the gate voltage of the output transistor such that the voltage difference between the gate of the output transistor and the input terminal exhibits a predetermined clamp voltage or more.

Abstract translation: 输出晶体管设置在输入端和输出端之间。 误差放大器调节输出晶体管的栅极电压，使得对应于输出电压的电压接近预定的参考电压。 在从输入端子到接地端子的路径上设置有波动检测电容器，将其一端设定为固定电压。 电流反馈电路向输出晶体管的栅极提供对应于流经波动检测电容器的电流的电流。 钳位电路钳位输出晶体管的栅极电压。 钳位电路30钳位输出晶体管的栅极电压，使得输出晶体管的栅极与输入端子之间的电压差表现出预定的钳位电压以上。

公开(公告)号：US20090273331A1

公开(公告)日：2009-11-05

申请号：US12096745

申请日：2006-12-06

Applicant: Hiroki Inoue

Inventor： Hiroki Inoue

IPC: G05F3/24

CPC classification number: G05F1/575

Abstract: An output transistor is provided between an input terminal and an output terminal. An error amplifier adjusts the gate voltage of the output transistor such that the voltage that corresponds to the output voltage approaches a predetermined reference voltage. A fluctuation detection capacitor is provided on a path from the input terminal to a grounded terminal, which sets one terminal thereof to a fixed voltage. A current feedback circuit supplies, to the gate of the output transistor, the current that corresponds to the current that flows through the fluctuation detection capacitor. A clamp circuit clamps the gate voltage of the output transistor. The clamp circuit 30 clamps the gate voltage of the output transistor such that the voltage difference between the gate of the output transistor and the input terminal exhibits a predetermined clamp voltage or more.

Abstract translation: 输出晶体管设置在输入端和输出端之间。 误差放大器调节输出晶体管的栅极电压，使得对应于输出电压的电压接近预定的参考电压。 在从输入端子到接地端子的路径上设置有波动检测电容器，将其一端设定为固定电压。 电流反馈电路向输出晶体管的栅极提供对应于流经波动检测电容器的电流的电流。 钳位电路钳位输出晶体管的栅极电压。 钳位电路30钳位输出晶体管的栅极电压，使得输出晶体管的栅极与输入端子之间的电压差表现出预定的钳位电压以上。