公开(公告)号：DE2961670D1

公开(公告)日：1982-02-18

申请号：DE2961670

申请日：1979-06-01

Applicant: IBM

Inventor： BEDERMAN SEYMOUR

IPC: G06F12/00 ,  G06F12/06 ,  G06F13/18 ,  G06F15/167 ,  G06F15/16 ,  G06F13/00

Abstract: A multiprocessor system is described which allows for the sharing of memories between the individual processors having synchronous memory interfaces. Three processing units are shown by way of example, each processor having its own local, associated memory. Two of the processing units can each access its own memory but not any other memory. The third processing unit can access its own memory as well as the memories associated with the other two processing units. An engine interface adapter interconnects the I/O busses of the processing units. The functions performed by the engine interface adapter can be divided into two principal groups. The first group of functions permits communication between the processors via their I/O busses. The second group of functions permits the aforedescribed sharing of the memory units between the processing units.

公开(公告)号：CA879357A

公开(公告)日：1971-08-24

申请号：CA879357D

Applicant: IBM

Inventor： LANKFORD LARRY G ,  BEDERMAN SEYMOUR

公开(公告)号：DE3785883D1

公开(公告)日：1993-06-24

申请号：DE3785883

申请日：1987-02-03

Applicant: IBM

Inventor： BEDERMAN SEYMOUR ,  WILLETT RICHARD MICHAEL

IPC: H04L12/46 ,  H04L12/56

Abstract: A method for configuring/reconfiguring a limited broadcast route within a bridge-connected network. The method includes an algorithm, which configures a minimum spanning tree route. A source node generates and transmits a search frame with indicia set to a value representative of a configuration time. Each bridge in the network receives the frame and determines if the setting of the indicia matches the setting of a time code in said bridge. If there is a match, the bridge discards the frame. Otherwise, the frame is forwarded and the bridge is characterized as a limited broadcast (LB) bridge. The process is repeated at subsequent bridges until a leaf bridge is determined. Thereafter, broadcast messages are permitted to advance through the LB bridges.

公开(公告)号：CA1158737A

公开(公告)日：1983-12-13

申请号：CA325546

申请日：1979-04-11

Applicant: IBM

Inventor： BEDERMAN SEYMOUR

IPC: G06F12/00 ,  G06F12/06 ,  G06F13/18 ,  G06F15/167 ,  G06F13/00 ,  G06F15/16

Abstract: SHARED SYNCHRONOUS MEMORY MULTIPROCESSING ARRANGEMENT A multiprocessor system is described which allows for the sharing of memories between the individual processors having synchronous memory interfaces. Three processing units are shown by way of example, each processor having its own local, associated memory. Two of the processing units can each access its own memory but not any other memory. The third processing unit can access its own memory as well as the memories associated with the other two processing units. A processor interface adapter interconnects the I/O busses of the processing units. The functions performed by the processor interface adapter can be divided into two principal groups. The first group of functions permits communication between the processors via their I/O busses. The second group of functions permits the aforedescribed sharing of the memory units between the processing units. FI9-77-050

公开(公告)号：AU528774B2

公开(公告)日：1983-05-12

申请号：AU4698979

申请日：1979-05-14

Applicant: IBM

Inventor： BEDERMAN SEYMOUR

IPC: G06F12/00 ,  G06F12/06 ,  G06F13/18 ,  G06F15/167 ,  G06F9/18 ,  G06F13/00 ,  G06F15/16

Abstract: A multiprocessor system is described which allows for the sharing of memories between the individual processors having synchronous memory interfaces. Three processing units are shown by way of example, each processor having its own local, associated memory. Two of the processing units can each access its own memory but not any other memory. The third processing unit can access its own memory as well as the memories associated with the other two processing units. An engine interface adapter interconnects the I/O busses of the processing units. The functions performed by the engine interface adapter can be divided into two principal groups. The first group of functions permits communication between the processors via their I/O busses. The second group of functions permits the aforedescribed sharing of the memory units between the processing units.

公开(公告)号：AU4698979A

公开(公告)日：1979-12-20

申请号：AU4698979

申请日：1979-05-14

Applicant: IBM

Inventor： BEDERMAN SEYMOUR

IPC: G06F12/00 ,  G06F12/06 ,  G06F13/18 ,  G06F15/167 ,  G06F9/18 ,  G06F13/00 ,  G06F15/16

Abstract: A multiprocessor system is described which allows for the sharing of memories between the individual processors having synchronous memory interfaces. Three processing units are shown by way of example, each processor having its own local, associated memory. Two of the processing units can each access its own memory but not any other memory. The third processing unit can access its own memory as well as the memories associated with the other two processing units. An engine interface adapter interconnects the I/O busses of the processing units. The functions performed by the engine interface adapter can be divided into two principal groups. The first group of functions permits communication between the processors via their I/O busses. The second group of functions permits the aforedescribed sharing of the memory units between the processing units.

公开(公告)号：CA895567A

公开(公告)日：1972-03-14

申请号：CA895567D

Applicant: IBM

Inventor： BEDERMAN SEYMOUR ,  LANKFORD LARRY G