公开(公告)号：JP2006253684A

公开(公告)日：2006-09-21

申请号：JP2006061418

申请日：2006-03-07

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHENG KANGGUO ,  RAMACHANDRA DEIBAKARUNI ,  HO HERBERT L ,  KARL J REEDENSU

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/76 ,  H01L21/762 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/06 ,  H01L27/08 ,  H01L27/108 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L21/84 ,  H01L27/10864 ,  H01L27/10867 ,  H01L27/1087 ,  H01L27/1203 ,  H01L29/66181 ,  H01L29/945

Abstract: PROBLEM TO BE SOLVED: To provides a structure including a trench capacitor array at least part of which is arranged under an embedded oxide layer of an SOI substrate.
SOLUTION: Each trench capacitor shares a common unitary embedded capacitor plate including at least part of a first unitary semiconductor region arranged under an embedded oxide layer. An upper boundary of the embedded capacitor plate defines a plane extending laterally over the whole trench capacitor array parallel to the major surface of a substrate. In a particular embodiment starting at an SOI substrate or a bulk substrate, the trench array and contact holes are formed at the same time such that the contact holes extend in the same depth as that of the trenches. Preferably, the width of the contact hole is substantially large compared with that of the trench, thereby forming conductive contact vias at the same time by processing used for forming a trench capacitor extending along the wall of the trench.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种包括沟槽电容器阵列的结构，其至少一部分布置在SOI衬底的嵌入式氧化物层的下方。 解决方案：每个沟槽电容器共享共同的单一嵌入式电容器板，其包括布置在嵌入式氧化物层下方的第一单元半导体区域的至少一部分。 嵌入式电容器板的上边界限定了平行于衬底的主表面的整个沟槽电容器阵列上横向延伸的平面。 在从SOI衬底或体衬底开始的特定实施例中，沟槽阵列和接触孔同时形成，使得接触孔在与沟槽的深度相同的深度上延伸。 优选地，接触孔的宽度与沟槽的宽度相比基本上大，由此通过用于形成沿沟槽壁延伸的沟槽电容器的处理同时形成导电接触孔。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2011066406A

公开(公告)日：2011-03-31

申请号：JP2010197286

申请日：2010-09-03

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DORIS BRUCE B ,  CHENG KANGGUO ,  WONG KEITH KWONG HON

IPC: H01L21/8238 ,  H01L21/28 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L21/823807 ,  H01L21/823842 ,  H01L21/823857

Abstract: PROBLEM TO BE SOLVED: To provide a PFET including a channel formed of SiGe, and including a metal gate and a high-k gate dielectric. SOLUTION: An SiGe layer 10 is epitaxially grown on an Si surface; a high-k dielectric and a metal are blanket-arranged on a SiGe layer; gatestacks are formed; thereafter a gate dielectric on an NFET side and the SiGe layer are removed; and a second high-k dielectric 53 and a second metal 52 are arranged. A PFET comprises a gate dielectric having a high-k dielectric on an SiGe channel 10, a gate containing a metal, and a source/drain having silicide. The NFET comprises the second high-k dielectric 53, a gate including the second metal 52, and a source/drain having silicide. An epitaxial SiGe layer on a substrate surface is formed only in a channel of the PFET. PFET and NFET device parameters can be separately optimized by compositions of the respective gate dielectrics and gatestacks. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供包括由SiGe形成的沟道并包括金属栅极和高k栅极电介质的PFET的PFET。 解决方案：SiGe层10在Si表面上外延生长; 高k电介质和金属被覆盖布置在SiGe层上; gatestacks形成; 此后去除NFET侧的栅电介质和SiGe层; 并且布置有第二高k电介质53和第二金属52。 PFET包括在SiGe沟道10上具有高k电介质的栅极电介质，含有金属的栅极和具有硅化物的源极/漏极。 NFET包括第二高k电介质53，包括第二金属52的栅极和具有硅化物的源极/漏极。 衬底表面上的外延SiGe层仅形成在PFET的沟道中。 PFET和NFET器件参数可以通过相应栅极电介质和放样的组成分别进行优化。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2007258702A

公开(公告)日：2007-10-04

申请号：JP2007062243

申请日：2007-03-12

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHENG KANGGUO ,  KHAN BABAR ALI

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/1087

Abstract: PROBLEM TO BE SOLVED: To provide a DRAM cell having a self-aligned gradient P well and a method for forming the same.
SOLUTION: The DRAM cell includes: (a) a semiconductor substrate; (b) an electrically conductive region containing a first portion, a second portion, and a third portion; (c) a first doped semiconductor region insulated from the first portion by a capacitor dielectric layer, surrounding the first portion; and (d) a second doped semiconductor region insulated from the second portion by a collar dielectric layer, surrounding the second portion. The second portion is positioned on the first portion and is electrically connected to the first portion, the third portion is positioned on the second portion and is electrically connected to the second portion. The collar dielectric layer is directly contacted with a capacitor dielectric layer. If it departs from the collar dielectric layer, the doping concentration of a second doped semiconductor region decreases.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供具有自对准梯度P阱的DRAM单元及其形成方法。 解决方案：DRAM单元包括：（a）半导体衬底; （b）包含第一部分，第二部分和第三部分的导电区域; （c）通过电容器介电层与第一部分绝缘的第一掺杂半导体区域，围绕第一部分; 和（d）第二掺杂半导体区域，所述第二掺杂半导体区域围绕所述第二部分由环形介电层与所述第二部分绝缘。 第二部分位于第一部分上并且电连接到第一部分，第三部分位于第二部分上并且电连接到第二部分。 套环电介质层与电容器电介质层直接接触。 如果它离开套环电介质层，则第二掺杂半导体区域的掺杂浓度降低。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2006041516A

公开(公告)日：2006-02-09

申请号：JP2005208400

申请日：2005-07-19

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHENG KANGGUO ,  RAMACHANDORA DEIVAKARUNI

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/786

CPC classification number: H01L29/1054 ,  H01L21/823412 ,  H01L29/739 ,  H01L29/78687

Abstract: PROBLEM TO BE SOLVED: To provide a method and a structure for forming strained and non-strained areas on one substrate. SOLUTION: A disclosed method comprises: a process of forming a pattern of strained and relaxed materials on a substrate 101; a process of forming a strained device 129 in the strained material; and a process of forming a non-strained device 131 in the relaxed material. The strained material is silicon (Si) in a tensile or compressive state, and the relaxed material is Si in a normal state. A buffer layer 113 which is made of silicon germanium (SiGe), silicon carbon (SiC), or a similar material and has a different lattice constant/structure from that of the substrate, and a relaxed layer 111 are formed on the substrate 101. The strained material is placed in the tensile or compressive state. In another embodiment, carbon-doped silicon or germanium-doped silicon is used to form the strained material. The structure includes a multilayer substrate having strained and non-strained materials on which a pattern is formed. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供在一个基板上形成应变和非应变区域的方法和结构。 解决方案：所公开的方法包括：在衬底101上形成应变和松弛材料的图案的工艺; 在应变材料中形成应变器件129的工艺; 以及在松弛材料中形成非应变器件131的工艺。 应变材料是处于拉伸或压缩状态的硅（Si），松弛材料是Si处于正常状态。 在衬底101上形成由硅锗（SiGe），硅碳（SiC）或类似材料制成并且具有与衬底的晶格常数/结构不同的晶格常数/结构的缓冲层113。 应变材料处于拉伸或压缩状态。 在另一个实施例中，使用碳掺杂硅或锗掺杂硅来形成应变材料。 该结构包括具有应变和非应变材料的多层基底，其上形成图案。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2008219002A

公开(公告)日：2008-09-18

申请号：JP2008035478

申请日：2008-02-18

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： MANDELMAN JACK ALLAN ,  LOUIS LU-CHEN HSU ,  CHENG KANGGUO ,  SHEETS JOHN EDWARD II

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L29/045 ,  H01L29/66818

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a FinFET having a short fin having a uniform width. SOLUTION: There are provided a fin with a comparatively uniform width in a fin-type field effect transistor (FinFET) 100 and a device and a method for forming the same. A fin structure 110 can be formed so that the surface of a sidewall part of the fin structure is vertical with respect to a first crystal direction. A tapered region at the end portion of the fin structure can be vertical with respect to a second crystal direction. The fin structure can be subjected to a crystal-dependent etching. For a crystal-dependent etching, a material can be removed relatively quickly from the part of the fin vertical to the second crystal direction, and due to this, a fin structure with a comparatively uniform width can be brought about. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种形成具有均匀宽度的短鳍的FinFET的方法。 解决方案：在翅片型场效应晶体管（FinFET）100中提供了具有相对均匀宽度的鳍片，以及用于形成该鳍片的器件及其方法。 翅片结构110可以形成为使翅片结构的侧壁部分的表面相对于第一晶体方向垂直。 翅片结构的端部处的锥形区域可相对于第二晶体方向垂直。 翅片结构可以进行晶体依赖蚀刻。 对于晶体依赖的蚀刻，可以从翅片垂直于第二晶体方向的部分相对快速地去除材料，并且由此可以产生具有相对均匀的宽度的翅片结构。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007335860A

公开(公告)日：2007-12-27

申请号：JP2007150183

申请日：2007-06-06

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： RADENS CARL JOHN ,  RAMACHANDRA DIVAKARUNI ,  CHENG KANGGUO

IPC: H01L21/822 ,  H01L27/04

CPC classification number: H01L29/945 ,  H01L29/66931

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor structure and a method for forming the same. SOLUTION: The semiconductor structure includes a semiconductor substrate. The semiconductor structure further includes an electrically insulating region on top of the semiconductor substrate. The semiconductor structure further includes a first semiconductor region on top of and in direct physical contact with the semiconductor substrate. The semiconductor structure further includes a second semiconductor region on top of the insulating region. The semiconductor structure further includes a capacitor in the first semiconductor region and the semiconductor substrate. The semiconductor structure further includes a capacitor electrode contact in the second semiconductor region and the electrically insulating region. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 解决的问题：提供一种半导体结构及其形成方法。 解决方案：半导体结构包括半导体衬底。 半导体结构还包括在半导体衬底的顶部上的电绝缘区域。 半导体结构还包括在半导体衬底之上并与之直接物理接触的第一半导体区域。 半导体结构还包括在绝缘区域的顶部上的第二半导体区域。 半导体结构还包括在第一半导体区域和半导体衬底中的电容器。 半导体结构还包括在第二半导体区域和电绝缘区域中的电容器电极接触。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007123893A

公开(公告)日：2007-05-17

申请号：JP2006290462

申请日：2006-10-25

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： MANDELMAN JACK A ,  CHENG KANGGUO

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10841 ,  G11C11/403 ,  G11C11/405 ,  H01L27/0207 ,  H01L27/10864 ,  H01L27/10894 ,  H01L29/045

Abstract: PROBLEM TO BE SOLVED: To provide improved gain and cell and a method for manufacturing and using the same. SOLUTION: In a first embodiment, the memory cell of a substrate containing (1) a PFET having almost planar orientation to the surface of the substrate and (2) an NFET coupled to an almost planar PFET is provided. The orientation of the NFET inside the substrate is almost vertical to that of the PFET. The invention includes many other embodiments. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供改进的增益和电池及其制造和使用方法。 解决方案：在第一实施例中，提供了一种衬底的存储单元，其包含（1）具有与衬底表面几乎平面取向的PFET和（2）耦合到几乎平面的PFET的NFET。 衬底内部NFET的取向几乎与PFET垂直。 本发明包括许多其它实施例。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：WO2009120612A2

公开(公告)日：2009-10-01

申请号：PCT/US2009037910

申请日：2009-03-23

Applicant: IBM ,  CHENG KANGGUO ,  RADENS CARL

Inventor： CHENG KANGGUO ,  RADENS CARL

IPC: H01L21/8238 ,  G06F9/45 ,  G06F17/50 ,  H01L29/76 ,  H01L29/94 ,  H01L31/00

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: A semiconductor device having a tensile and/or compressive strain applied thereto and methods of manufacturing the semiconductor devices and design structure to enhance channel strain. The method includes forming a gate structure for an NFET and a PFET and forming sidewalls on the gate structure for the NFET and the PFET using a same deposition and etching process. The method also includes providing stress materials in the source and drain regions of the NFET and the PFET.

Abstract translation: 施加有拉伸和/或压缩应变的半导体器件以及制造半导体器件和设计结构以增强沟道应变的方法。 该方法包括形成用于NFET和PFET的栅极结构，并且使用相同的沉积和蚀刻工艺在用于NFET和PFET的栅极结构上形成侧壁。 该方法还包括在NFET和PFET的源极和漏极区中提供应力材料。

公开(公告)号：WO2011019562A2

公开(公告)日：2011-02-17

申请号：PCT/US2010044385

申请日：2010-08-04

Applicant: IBM ,  BOOTH ROGER A ,  CHENG KANGGUO ,  KOTHANDARAMAN CHANDRASEKHARAN

Inventor： BOOTH ROGER A ,  CHENG KANGGUO ,  KOTHANDARAMAN CHANDRASEKHARAN

IPC: H01L23/62 ,  H01L21/82

CPC classification number: H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method forms an anti-fuse structure comprises a plurality of parallel conductive fins positioned on a substrate, each of the fins has a first end and a second end. A second electrical conductor is electrically connected to the second end of the fins. An insulator covers the first end of the fins and a first electrical conductor is positioned on the insulator. The first electrical conductor is electrically insulated from the first end of the fins by the insulator. The insulator is formed to a thickness sufficient to break down on the application of a predetermined voltage between the second electrical conductor and the first electrical conductor and thereby form an uninterrupted electrical connection between the second electrical conductor and the first electrical conductor through the fins.

Abstract translation: 一种形成抗熔丝结构的方法包括位于基板上的多个平行的导电翅片，每个翼片具有第一端和第二端。 第二电导体电连接到散热片的第二端。 绝缘体覆盖翅片的第一端并且第一电导体位于绝缘体上。 第一电导体通过绝缘体与散热片的第一端电绝缘。 绝缘体形成为足以在第二电导体和第一电导体之间施加预定电压时分解的厚度，从而通过翅片在第二电导体和第一电导体之间形成不间断的电连接。

公开(公告)号：JP2011101002A

公开(公告)日：2011-05-19

申请号：JP2010238380

申请日：2010-10-25

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHENG KANGGUO ,  FALTERMEIER JONATHAN E ,  BASKER VEERARAGHAVAN S ,  DORIS BRUCE B

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L29/66795 ,  H01L21/26586 ,  H01L21/823431 ,  H01L29/66803 ,  H01L29/785

Abstract: PROBLEM TO BE SOLVED: To provide a reliable process for achieving selectivity for selectively etching spacer/side wall material on fin against spacer/side wall material on a gate stack of finFET structure in an integrated circuit. SOLUTION: A spacer material is deposited in conformal manner on both fin and gate stack. Inclined impurity injection is performed almost parallel to the gate stack so that only the spacer material deposited on the fin is selectively damaged. Thus, such finFET is provided as covers a part of fin of the semiconductor material formed on a substrate and contains a spacer having substantially uniform profile along the length of the gate stack. By a damage caused by inclined injection, the spacer material on the fin can be so etched as has a higher selectivity than the spacer material on the gate stack. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供一种可靠的方法，用于实现在集成电路中在finFET结构的栅叠层上选择性地蚀刻翅片上的间隔件/侧壁材料的隔离物/侧壁材料的选择性。 解决方案：隔板材料以共形方式沉积在散热片和栅极叠层上。 倾斜的杂质注入与栅极堆叠几乎平行地进行，使得仅沉积在鳍上的间隔物被选择性地损坏。 因此，这种finFET被设置为覆盖形成在衬底上的半导体材料的鳍片的一部分，并且包含沿着栅极堆叠的长度具有基本均匀轮廓的间隔物。 由于倾斜注射造成的损伤，翅片上的间隔物材料可以被蚀刻，具有比栅极叠层上的间隔物材料更高的选择性。 版权所有（C）2011，JPO＆INPIT