公开(公告)号：ES2072895T3

公开(公告)日：1995-08-01

申请号：ES89302162

申请日：1989-03-03

Applicant: IBM

Inventor： BEGUN RALPH MURRAY ,  BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

IPC: G06F9/44 ,  G06F9/445 ,  G06F13/36 ,  G06F13/362

Abstract: A multi-bus microcomputer system includes a cache subsystem and an arbitration supervisor. A CPU is provided with a PREEMPT signal source which generates a preempt signal in CPU cycles extending beyond a specified duration. The preempt signal is effective at any device having access to the bus to initiate an orderly termination of the bus usage. When that device signals its termination of bus usage, the arbitration supervisor changes the state of an ARB/GRANT conductor, which had been in the grant phase, to the arbitration phase. During the arbitration phase each of the devices (other than the CPU) cooperates in an arbitration mechanism for bus usage during the next grant phase. On the other hand, the CPU, having asserted preempt, responds to a signal indicating initiation of the arbitration phase by immediately accessing the system bus.

公开(公告)号：AT125051T

公开(公告)日：1995-07-15

申请号：AT89302135

申请日：1989-03-03

Applicant: IBM

Inventor： BEGUN RALPH MURRAY ,  BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

IPC: G06F12/08

Abstract: A microcomputer system includes a microprocessor, a cache memroy, and a cache controller all coupled to a local bus. The local bus is coupled to a sytem bus, connecting the remaining system components, through latches. When writing data, the microcomputer can perform a posted write to a unit on the system bus by writing the data into the latches and then, on receipt of a ready signal from the cache controller, continuing its operations without waiting for the data to pas to its destination. A problem arises if the data is posted to a unit with a data width less than that of the microprocessor. In this case, the data should be sent in multiple cycles, but the read signal is generated before the data width of the unit is known and the microprocessor then continues its operations and can not, therefore, transmit the data correctly. To solve this problem, a logic unit is added to monitor the ready signal and the output of a decoder which detects non-cacheable addresses (which are of data width different from the microprocessor data width). If a non-cacheable address is detected, the read signal from the cache controller through the logic unit is withheld from the microprocessor, which now waits to continue processing beyond the write until a ready signal is received from the addressed unit on the system bus.

公开(公告)号：IN175457B

公开(公告)日：1995-06-17

申请号：IN44DE1989D

申请日：1989-05-19

Applicant: IBM

Inventor： BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

IPC: G00F15/00

公开(公告)号：DE68918754T2

公开(公告)日：1995-04-27

申请号：DE68918754

申请日：1989-05-25

Applicant: IBM

Inventor： BEGUN RALPH MURRAY ,  BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

IPC: G06F9/38 ,  G06F12/08

Abstract: In a microcomputer system comprising a microprocessor and a cache subsystem and operable in a pipelined mode, there is potential incompatibility between pipelined operations and dynamic bus sizing as the cache subsystem operates with a fixed size data width and dynamic bus sizing allows the system to operate with devices of differing data width. This incompatibility is accommodated by the present system by defining certain addresses as cacheable addresses and other addresses as non-cacheable addresses and ensuring that addresses of devices of data width different from the cache data width are non-cacheable. An address decoder provides a control signal indicating whether or not a generated address is within the cacheable range. This control signal controls a next address signal applied to the microprocessor, which signal allows the processor to proceed to a following cycle prior to the end of the current cycle. Whenever a non-cacheable address is detected, the next address signal is suppressed.

公开(公告)号：NO175837B

公开(公告)日：1994-09-05

申请号：NO891583

申请日：1989-04-18

Applicant: IBM

Inventor： BEGUN RALPH MURRAY ,  BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

IPC: G06F12/08 ,  G06F12/06 ,  G06F13/38

Abstract: In a dual bus microcomputer system using a cache memory and a cache controller, the timing requirements placed on non-cache memory components by the cache controller are more stringent than the timing requirements placed on the non-cache memory components by the microprocessor. A logic circuit operates on the cache write enable (CWE) signals, and delays those signals in the event of a cache read miss. Delaying the CWE signals relaxes the timing requirements placed on non-cache memory components and at the same time does not impact wait state parameters for read miss operations.

公开(公告)号：NO174788B

公开(公告)日：1994-03-28

申请号：NO891584

申请日：1989-04-18

Applicant: IBM

Inventor： BEGUN RALPH MURRAY ,  BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

IPC: G06F9/38 ,  G06F12/08 ,  G06F12/06

Abstract: In a microcomputer system comprising a microprocessor and a cache subsystem and operable in a pipelined mode, there is potential incompatibility between pipelined operations and dynamic bus sizing as the cache subsystem operates with a fixed size data width and dynamic bus sizing allows the system to operate with devices of differing data width. This incompatibility is accommodated by the present system by defining certain addresses as cacheable addresses and other addresses as non-cacheable addresses and ensuring that addresses of devices of data width different from the cache data width are non-cacheable. An address decoder provides a control signal indicating whether or not a generated address is within the cacheable range. This control signal controls a next address signal applied to the microprocessor, which signal allows the processor to proceed to a following cycle prior to the end of the current cycle. Whenever a non-cacheable address is detected, the next address signal is suppressed.

公开(公告)号：MX171578B

公开(公告)日：1993-11-08

申请号：MX1619989

申请日：1989-05-26

Applicant: IBM

Inventor： BLAND PATRICK MAURICE ,  DEAN MARK EDWARD ,  MILLING PHILIP ERNA

IPC: G06F9/44 ,  G06F9/445 ,  G06F13/36 ,  G06F13/362 ,  G06F7/06

Abstract: A multi-bus microcomputer system includes a cache subsystem and an arbitration supervisor. A CPU is provided with a PREEMPT signal source which generates a preempt signal in CPU cycles extending beyond a specified duration. The preempt signal is effective at any device having access to the bus to initiate an orderly termination of the bus usage. When that device signals its termination of bus usage, the arbitration supervisor changes the state of an ARB/GRANT conductor, which had been in the grant phase, to the arbitration phase. During the arbitration phase each of the devices (other than the CPU) cooperates in an arbitration mechanism for bus usage during the next grant phase. On the other hand, the CPU, having asserted preempt, responds to a signal indicating initiation of the arbitration phase by immediately accessing the system bus.

公开(公告)号：HK11592A

公开(公告)日：1992-02-21

申请号：HK11592

申请日：1992-02-13

Applicant: IBM

Inventor： BEGUN RALPH MURRAY ,  BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

IPC: G06F12/08

Abstract: In a dual bus microcomputer system using a cache memory and a cache controller, the timing requirements placed on non-cache memory components by the cache controller are more stringent than the timing requirements placed on the non-cache memory components by the microprocessor. A logic circuit operates on the cache write enable (CWE) signals, and delays those signals in the event of a cache read miss. Delaying the CWE signals relaxes the timing requirements placed on non-cache memory components and at the same time does not impact wait state parameters for read miss operations.

公开(公告)号：HK11492A

公开(公告)日：1992-02-21

申请号：HK11492

申请日：1992-02-13

Applicant: IBM

Inventor： BEGUN RALPH MURRAY ,  BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

IPC: G06F9/38 ,  G06F12/08

Abstract: In a microcomputer system comprising a microprocessor and a cache subsystem and operable in a pipelined mode, there is potential incompatibility between pipelined operations and dynamic bus sizing as the cache subsystem operates with a fixed size data width and dynamic bus sizing allows the system to operate with devices of differing data width. This incompatibility is accommodated by the present system by defining certain addresses as cacheable addresses and other addresses as non-cacheable addresses and ensuring that addresses of devices of data width different from the cache data width are non-cacheable. An address decoder provides a control signal indicating whether or not a generated address is within the cacheable range. This control signal controls a next address signal applied to the microprocessor, which signal allows the processor to proceed to a following cycle prior to the end of the current cycle. Whenever a non-cacheable address is detected, the next address signal is suppressed.

公开(公告)号：AU615055B2

公开(公告)日：1991-09-19

申请号：AU3409989

申请日：1989-05-05

Applicant: IBM

Inventor： BEGUN RALPH MURRAY ,  BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

IPC: G06F9/38 ,  G06F12/08

Abstract: In a microcomputer system comprising a microprocessor and a cache subsystem and operable in a pipelined mode, there is potential incompatibility between pipelined operations and dynamic bus sizing as the cache subsystem operates with a fixed size data width and dynamic bus sizing allows the system to operate with devices of differing data width. This incompatibility is accommodated by the present system by defining certain addresses as cacheable addresses and other addresses as non-cacheable addresses and ensuring that addresses of devices of data width different from the cache data width are non-cacheable. An address decoder provides a control signal indicating whether or not a generated address is within the cacheable range. This control signal controls a next address signal applied to the microprocessor, which signal allows the processor to proceed to a following cycle prior to the end of the current cycle. Whenever a non-cacheable address is detected, the next address signal is suppressed.