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11.发明专利
公开(公告)号：DE3367995D1
公开(公告)日：1987-01-15
申请号：DE3367995
申请日：1983-12-21
Applicant: IBM
Inventor： GILLETT JOHN BRIAN , MIRAGLIA JOHN ALBERT
Abstract: An electronic component assembly including a printed circuit board unit and a protective cover wherein the cover has flexible flap portions that protect electrical contact pads disposed along at least one edge of the printed circuit board unit. The flap portions can be flexed to expose the electrical contact pads. Removal of the flexing force allows the flaps to return to their relaxed, closed positon by means of the internal resiliency of the cover material. Such flexing of the flap portions can be effected by surfaces of a corresponding mating connector so as to expose the contact pads to the contact pins of the mating connector. When the electronic component assembly is removed from the mating connector, the printed circuit board unit is contained by (i.e., completely surrounded by) the cover thereby protecting the unit from physical impact or dust.
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公开(公告)号：DE68912274T2
公开(公告)日：1994-06-30
申请号：DE68912274
申请日：1989-10-03
Applicant: IBM
Inventor： GILLETT JOHN BRIAN , LOHREY FRED HELMUT , LORENZEN JERRY ALAN
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公开(公告)号：GB1126489A
公开(公告)日：1968-09-05
申请号：GB78366
申请日：1966-01-07
Applicant: IBM
Inventor： TAUB DANIEL MATTHEW , SOWTER BRIAN RAYMOND , BETTS ALAN JOHN , GILLETT JOHN BRIAN
Abstract: 1,126,489. Tri-stable circuits. INTERNATIONAL BUSINESS MACHINES CORP. 12 Aug., 1966 [7 Jan., 1966], No. 783/66. Heading H3T. A tri-stable circuit comprises two crosscoupled identical bi-stable circuits, two states having the bi-stable circuits in opposite states and the third state having the bi-stable circuits in the same state, the triggering threshold for switching from the third state being less than the threshold for switching from the first or second state. Such a circuit is used for reading the bipolar output of a computer store, as when switched into its first or second state the second pulse of the pair is unable to overcome the greater threshold for switching back and cannot therefore give a false output. First circuit (Fig. 2).-A pair of silicon transistors T1 is cross-coupled by silicon diodes D3, and each transistor has a negative feedback path through a pair of germanium tunnel diodes D1, D2 (or a single gallium arsenide tunnel diode). Initially both transistors T1 are conducting and the tunnel diodes are in their low-voltage state. The input is applied differentially to the bases of T2 and T2 1 so that the collector current of the former will rise and increase the current through the diodes D1, D2 to switch them to their high-voltage state. The collector voltage of T1 rises but is clamped by conduction of D3, and the base voltage therefore falls to cut off T1. At the end of the input pulse the currents in T2 and T2 1 revert to their former values, but D1, D2 remain in their high-voltage state and part of the current through D3 flows through D1 1 , D2 1 in the reverse direction, D3 1 remaining cut off. This ensures that D1 1 , D2 1 will not be switched by the subsequent positive pulse on T2 1 . The circuit is reset by injecting current into the collectors of T2 and T2 1 to switch the tunnel diodes to their low-voltage state. The output is taken from the collectors of T 1 and T1 1 . Second circuit (Fig. 4).-Tunnel diodes D4, D4 1 are held initially in the low-voltage state by currents through transistors T3, T3 1 which are determined by a Zener diode D5 associated with temperature-compensating transistor T7. Zener diodes D6, D6 1 are permanently conducting through resistors R8, R8 1 and allow T4, T4 1 to supply additional current to the tunnel diodes so that they are biased just below the peak current point. Differential input signals at A and B decrease the current through T4 and D4, and increase the current through T4 1 and D4 1 , switching the latter to its high-voltage state. Transistor T5 1 then cuts off by the fall in its base potential and turns on T10 1 through resistor R10 1 . Transistor T6 1 also turns on and sends a current through D4 in the reverse direction so that it cannot be switched by a subsequent pulse of the opposite polarity at A. If the initial signal at B is large enough to out off T4 1 the currents through the tunnel diodes are maintained by T3 1 and T6 1 . If the initial signal at B is very large in the positive direction, the supply current for T4 1 is augmented by a transient path through T8 and C1 to supplement the current through T8 1 . The circuit is reset by a positive pulse at C which turns on T13 and cuts off T12. The rise in T12 collector voltage is passed through T11 to turn on T9 and T9 1 and cut off those transistos T5, T5 1 , T10, T10 1 which are not already off. T6 and T6 1 then both conduct and send reverse current through both tunnel diodes; these revert to their low-voltage state when the reset pulse ceases. An output is taken from D. At least transistors T3, T7, T8, T3 1 , T8 1 should be in the form of an integrated circuit to ensure temperature compensation. Third circuit (Fig. 6).-Transistors T15, T16, T18 and T15 1 , T16 1 , T18 1 form the individual bi-stable circuits. Initially T15, T15 1 , T17, T17 1 are conducting and T16, T16 1 , T18, T18 1 , T19, T19 1 are cut off. Differential input signals at A1, B1 are applied (via optional emitter followers T17, T17 1 ) to turn on either T16 or T16 1 . If T16 conducts it cuts off T15 and hence turns on T18 to allow current to flow through D10, R18 and R19. This latches T16 on and further increases the base potential of T15 1 so that the latter cannot be cut off by a subsequent pulse of opposite polarity which turns on T16 1 . The circuit is reset by a positive pulse at R which turns on T19 and T19 1 and cuts off T16 and T16 1 . The diodes D10, D10 1 may be omitted. An output is taken from OP.
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公开(公告)号：FR1523761A
公开(公告)日：1968-05-03
申请号：FR06008494
申请日：1967-05-09
Applicant: IBM
Inventor： GILLETT JOHN BRIAN
IPC: H01L21/74 , H01L27/00 , H01L27/07 , H01L27/082 , H03H11/48
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公开(公告)号：GB1081385A
公开(公告)日：1967-08-31
申请号：GB2892966
申请日：1966-06-28
Applicant: IBM
Inventor： GILLETT JOHN BRIAN
IPC: H01L21/74 , H01L27/00 , H01L27/07 , H01L27/082 , H03H11/48
Abstract: 1,081,385. Reactance circuits. INTERNATIONAL BUSINESS MACHINES CORPORATION. June 28, 1966, No. 28929/66. Heading H3R. [Also in Division H1] The circuit shown is equivalent to an inductance and may be manufactured as an integrated circuit. The capacitor C may be omitted (Fig. 3, not shown) and the resistance R may be replaced by a direct connection (Fig. 1, not shown). The emitter of T2 may be joined to the base of T1 through a resistance or through a F.E.T. having its gate connected to its source or drain. The transistors T1 and T2 may both be PNP types (Fig. 2, not shown).
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Patent Agency Ranking
公开(公告)号：GB1079630A
公开(公告)日：1967-08-16
申请号：GB2893066
申请日：1966-06-28
Applicant: IBM
Inventor： GILLETT JOHN BRIAN
IPC: H01L21/8222 , H01L27/07
Abstract: 1,079,630. Semi-conductor devices. INTERNATIONAL BUSINESS MACHINES CORPORATION. June 28, 1966, No. 28930/66. Heading H1K. The integrated differential amplifier shown functions as the equivalent of two transistors with emitters short-circuited and with resistors joined base-to-base and collector-to-collector. The effects of these interconnecting resistors may be minimized by control of the geometry and resistivity of the base and collector layers. The effect of inter-collector connection can be further minimized by cascading respective outputs with two transistors from the collectors of which the final difference signal is taken (Fig. 4, not shown). In a modified structure the emitter region is divided so that a third, centretap, base contact may be provided which in operation is connected to a source of reference potential. In the structure shown the collector region 2 is formed by epitaxial deposition of a 5Á thick layer with a dopant concentration of 10 16 atoms/cm. -3 , the emitter region is 1.2Á thick and the base region is 0À3 Á thick. The buried N + layers SC1, SC2 help keep the collector currents of the two halves separate.
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公开(公告)号：DE3477625D1
公开(公告)日：1989-05-11
申请号：DE3477625
申请日：1984-12-04
Applicant: IBM
Inventor： GILLETT JOHN BRIAN , MIRAGLIA JOHN ALBERT
Abstract: A ZIF connector for establishing an electrical connection between the I/O pads (110) of an edge-connected printed circuit board (100) and a set of printed conductors (13) may have one row of or two opposing rows of contacts (50), adjacent or both adjacent and opposite ones of the contacts having different lengths. An upper housing (30) has a plurality of cams (40) mounted thereon, each cam having a different cam surface profile (42). The surface profiles of the cams are staggered into two different lengths corresponding to the lengths of the contacts so that when the cams are actuated by imparting a vertical motion to the upper housing, the contacts will simultaneously engage the 1/0 pads in a staggered fashion. Moreover, the surface profiles of the cams are constructed so that after simultaneous engagement, the contacts perform sequential wipe cycles on the pads. The staggered and sequential wipe cycles promote the stability of the board within the connector without sacrificing electrical integrity.
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公开(公告)号：DE3370569D1
公开(公告)日：1987-04-30
申请号：DE3370569
申请日：1983-12-21
Applicant: IBM
Inventor： BOLAND LAWRENCE JOSEPH , GILLETT JOHN BRIAN
IPC: H01R12/89 , H05K1/11 , H01R13/193 , H01R23/68
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公开(公告)号：GB1199381A
公开(公告)日：1970-07-22
申请号：GB2076668
申请日：1968-05-02
Applicant: IBM
Inventor： GILLETT JOHN BRIAN
Abstract: 1,199,381. Magnetic storage arrangements. INTERNATIONAL BUSINESS MACHINES CORP. 2 May, 1968, No. 20766/68. Heading H3B. To non-destructively read out an anisotropic thin magnetic film storage element 13, Fig. 1, an A.C. of frequency f is applied to a word line 12 so that an A.C. of frequency 2f is induced in a bit line 11 having one of two possible phase positions depending on the digit stored, the capacitive coupled noise which is also developed in the bit line being used as a source of strobe signals to determine the identity of the digit read out. In the storage matrix 10 shown, a decoding tree 15, controlled from word select lines 16 through amplifiers 17, applies A.C. of frequency f to a selected word line 12 for both reading and writing. Further decoding trees 19, each provided for a different group of bit lines 11, are controlled by segment select lines 24 through amplifiers 23, and are effective to connect a selected bit line in a group to a bit driver 20 and a sense amplifier 21. For writing, word and bit drivers 14 and 20 are operative simultaneously, and apply A.C. of frequency f and 2f respectively to a selected storage element in a group, the phase position of the A.C. of frequency 2f from bit driver 20 determining the stable state along the easy axis of magnetization to be established in the storage element. For reading out from a selected element in a group, the appropriate bit line is coupled by the associated decoding tree 19 to the sense amplifier 21, the A.C. of frequency f from the word driver inducing A.C. of frequency 2f in the bit lines. In addition, each bit line of the group picks up capacitive noise of frequency f. The decoding tree passes the A.C. of frequency 2f in the bit line of the selected storage element to the sense amplifier and passes the capacitive noise in all the bit lines of the group to this amplifier. The phase position of the A.C. of frequency 2f is determined by the binary digit stored in the interrogated storage element, and the identity of the digit is determined by the sense amplifier circuit shown in Fig. 4 in which the frequencies f and 2f are segregated by bandpass filters 31 and 32, respectively. The capacitive noise through filter 31 generates strobe pulses of frequency 2f in a strobe 33, the strobe circuit being responsive to each zero of the capacitive noise of frequency f. The strobe pulses control a gate 35, and thus enable the phase position of the A.C. of frequency 2f from the interrogated storage element to be determined by an integrator 36 and threshold switch 37. The decoding trees, Fig. 3, each comprise a branching arrangement of parallel L-C circuits, each circuit being represented in the Figure by a square box. The inductor L of each L-C circuit has an associated control line A, #A ... C, and is saturated when its control line is D.C. energized. Each L-C circuit in the decoding tree 14 is resonant at frequency f when unsaturated, and in each decoding tree 19 is resonant at frequency 2f. Thus the associated word or bit driver is operatively connected to the required line by saturating selected L-C circuits in a decoding tree. In the case of the decoding trees 19, since the parallel L-C circuits connected to unselected bit lines have a high impedance at the resonant frequency 2f, but not at frequency f, the capacitive noise in each of the bit lines of a group is able to pass through the decoding tree and therefore act cumulatively in the sense amplifier.
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