公开(公告)号：AU2002219440A1

公开(公告)日：2002-07-30

申请号：AU2002219440

申请日：2002-01-14

Applicant: IBM

Inventor： MAIWALD DIETRICH ,  FURRER SIMEON ,  SCHOTT WOLFGANG

IPC: H04L12/28 ,  G06F12/08 ,  H04L12/56 ,  G06F9/46

Abstract: Communication device for processing outgoing and incoming packets. The device includes a plurality of signal processing units connected in sequence, each signal processing unit being clocked by a common clock signal. The device further includes a mode line connected to each signal processing unit for switching each signal processing unit between a transmit mode and a receive mode. The device further includes a control line to which each signal processing unit is connected. The control line communicating flow control information either in the transmit mode to at least one of the preceding signal processing units or in the receive mode to at least one of the following signal processing units.

公开(公告)号：CA2431134C

公开(公告)日：2007-07-03

申请号：CA2431134

申请日：2002-01-14

Applicant: IBM

Inventor： MAIWALD DIETRICH ,  FURRER SIMEON ,  SCHOTT WOLFGANG

IPC: H04L12/28 ,  H04L12/56 ,  H04L29/02

Abstract: The invention provides a baseband system for a short-range radio communicati on system. It is conform to the Bluetooth baseband specification and is well- suited for an efficient hardware implementation, providing a low-power, smal l- sized, and low-cost radio subsystem design. The baseband system comprises a transceiver unit and a buffer unit, whereby the system has an efficient gate count and a reduced power consumption. The transceiver unit design is based on a pipelined signal processing with distributed data path flow control. The transceiver unit processes outgoing and incoming packets, and comprises a plurality of signal processing units connected in sequence, whereby each signal processing unit is clocked by a common clock signal. A mode line is connected to each signal processing unit for switching each signal processin g unit between a transmit mode and a receive mode. A control line to which eac h signal processing unit is connected communicates flow control information either in the transmit mode to one or more of the preceding signal processin g units or in the receive mode to one or more of the following signal processi ng units. The buffer unit comprises a buffer system that applies a flexible memory organization concept, which leads to an efficient implementation of buffers or storage elements in terms of gate count and power consumption, an d offers the flexibility to dynamically allocate memory for variable length us er packets. The buffer system for storing data of the first processing unit and second processing unit comprises a plurality of storage elements, whereby ea ch storage element has a first storage unit and a second storage units. A switc h subsystem is provided for switching each storage element between first and second modes. In the first mode each first storage unit is addressable by th e first processing unit and each second storage unit is addressable by the second processing unit. In the second mode each second storage unit is addressable by the first processing unit and each first storage unit is addressable by the second processing unit.

公开(公告)号：DE602004006537D1

公开(公告)日：2007-06-28

申请号：DE602004006537

申请日：2004-11-19

Applicant: IBM

Inventor： FURRER SIMEON ,  JELITTO JENS ,  SCHOTT WOLFGANG ,  WEISS BEAT

IPC: H04L27/26 ,  G06F17/14

Abstract: The invention relates to a method for modulating sub-carrier symbols to an intermediate-frequency OFDM signal having even and odd samples, including following steps: transforming a number N of the sub-carrier symbols to pre-processed sub-carrier symbols; performing a complex inverse discrete Fourier transformation (IDFT) on the pre-processed sub-carrier symbols to generate complex output symbols; and transforming the complex output symbols to the intermediate-frequency OFDM signal, wherein the sub-carrier symbols are transformed so that the even and odd samples of the intermediate-frequency OFDM signal are given by real and imaginary parts of the complex output symbols.

公开(公告)号：AT362683T

公开(公告)日：2007-06-15

申请号：AT04798923

申请日：2004-11-19

Applicant: IBM

Inventor： FURRER SIMEON ,  JELITTO JENS ,  SCHOTT WOLFGANG ,  WEISS BEAT

IPC: H04L27/26 ,  G06F17/14

Abstract: The invention relates to a method for modulating sub-carrier symbols to an intermediate-frequency OFDM signal having even and odd samples, including following steps: transforming a number N of the sub-carrier symbols to pre-processed sub-carrier symbols; performing a complex inverse discrete Fourier transformation (IDFT) on the pre-processed sub-carrier symbols to generate complex output symbols; and transforming the complex output symbols to the intermediate-frequency OFDM signal, wherein the sub-carrier symbols are transformed so that the even and odd samples of the intermediate-frequency OFDM signal are given by real and imaginary parts of the complex output symbols.

公开(公告)号：DE60007487D1

公开(公告)日：2004-02-05

申请号：DE60007487

申请日：2000-06-03

Applicant: IBM

Inventor： GFELLER FRITZ ,  SCHOTT WOLFGANG

IPC: G06F11/00 ,  H04L1/00 ,  H04L1/08 ,  H04L1/20

公开(公告)号：CA2431134A1

公开(公告)日：2002-07-25

申请号：CA2431134

申请日：2002-01-14

Applicant: IBM

Inventor： SCHOTT WOLFGANG ,  FURRER SIMEON ,  MAIWALD DIETRICH

IPC: H04L12/28

Abstract: The invention provides a baseband system for a short-range radio communicati on system. It is conform to the Bluetooth baseband specification and is well- suited for an efficient hardware implementation, providing a low-power, smal l- sized, and low-cost radio subsystem design. The baseband system comprises a transceiver unit and a buffer unit, whereby the system has an efficient gate count and a reduced power consumption. The transceiver unit design is based on a pipelined signal processing with distributed data path flow control. The transceiver unit processes outgoing and incoming packets, and comprises a plurality of signal processing units connected in sequence, whereby each signal processing unit is clocked by a common clock signal. A mode line is connected to each signal processing unit for switching each signal processin g unit between a transmit mode and a receive mode. A control line to which eac h signal processing unit is connected communicates flow control information either in the transmit mode to one or more of the preceding signal processin g units or in the receive mode to one or more of the following signal processi ng units. The buffer unit comprises a buffer system that applies a flexible memory organization concept, which leads to an efficient implementation of buffers or storage elements in terms of gate count and power consumption, an d offers the flexibility to dynamically allocate memory for variable length us er packets. The buffer system for storing data of the first processing unit and second processing unit comprises a plurality of storage elements, whereby ea ch storage element has a first storage unit and a second storage units. A switc h subsystem is provided for switching each storage element between first and second modes. In the first mode each first storage unit is addressable by th e first processing unit and each second storage unit is addressable by the second processing unit. In the second mode each second storage unit is addressable by the first processing unit and each first storage unit is addressable by the second processing unit.