TRANSACTIONAL PROCESSING
    12.
    发明申请
    TRANSACTIONAL PROCESSING 审中-公开
    交易处理

    公开(公告)号:WO2013186721A3

    公开(公告)日:2014-05-30

    申请号:PCT/IB2013054812

    申请日:2013-06-12

    Applicant: IBM IBM UK

    CPC classification number: G06F9/467 G06F9/3004 G06F9/30087 G06F9/3834

    Abstract: A transaction is initiated via a transaction begin instruction. During execution of the transaction, the transaction may abort. If the transaction aborts, a determination is made as to the type of transaction. Based on the transaction being a first type of transaction, resuming execution at the transaction begin instruction, and based on the transaction being a second type, resuming execution at an instruction following the transaction begin instruction. Regardless of transaction type, resuming execution includes restoring one or more registers specified in the transaction begin instruction and discarding transactional stores. For one type of transaction, the nonconstrained transaction, the resuming includes storing information in a transaction diagnostic block.

    Abstract translation: 交易通过交易开始指令启动。 交易执行期间,交易可能会中止。 如果交易中止,则确定交易的类型。 基于事务是第一种类型的事务,在事务开始指令中恢复执行,并且基于该事务是第二类型,在事务开始指令之后的指令处恢复执行。 不管交易类型如何,恢复执行包括恢复在事务开始指令中指定的一个或多个寄存器,并丢弃事务存储。 对于一种类型的事务,非约束事务,恢复包括将信息存储在事务诊断块中。

    NEXT INSTRUCTION ACCESS INTENT INSTRUCTION
    13.
    发明申请
    NEXT INSTRUCTION ACCESS INTENT INSTRUCTION 审中-公开
    下一条指导访问指导

    公开(公告)号:WO2013186266A3

    公开(公告)日:2014-02-13

    申请号:PCT/EP2013062165

    申请日:2013-06-12

    Applicant: IBM IBM UK

    Abstract: Executing a Next Instruction Access Intent instruction by a computer. The processor obtains an access intent instruction indicating an access intent. The access intent is associated with an operand of a next sequential instruction. The access intent indicates usage of the operand by one or more instructions subsequent to the next sequential instruction. The computer executes the access intent instruction. The computer obtains the next sequential instruction. The computer executes the next sequential instruction, which comprises based on the access intent, adjusting one or more cache behaviors for the operand of the next sequential instruction.

    Abstract translation: 由计算机执行下一条指令访问意图指令。 处理器获得指示访问意图的访问意图指令。 访问意图与下一个顺序指令的操作数相关联。 访问意图表示在下一个顺序指令之后的一个或多个指令的操作数的使用。 计算机执行访问意图指令。 计算机获取下一个顺序指令。 计算机执行下一个顺序指令,其包括基于访问意图,调整下一个顺序指令的操作数的一个或多个缓存行为。

    COMPARE AND BRANCH FACILITY AND INSTRUCTION THEREFORE
    14.
    发明申请
    COMPARE AND BRANCH FACILITY AND INSTRUCTION THEREFORE 审中-公开
    比较和分支机构及其说明

    公开(公告)号:WO2009087158A4

    公开(公告)日:2009-11-12

    申请号:PCT/EP2009050105

    申请日:2009-01-07

    CPC classification number: G06F9/30058 G06F9/30094 G06F9/30167

    Abstract: An atomic compare and branch instruction is executed that combines the function of a compare instruction having an option field with a conditional branch or jump instruction such that condition codes are preserved rather than setting condition codes to a value representative of the compare results. One comparand is obtained from any one of a memory location or an immediate field and the other comparand is obtained from a register field.

    Abstract translation: 执行原子比较和分支指令,其将具有选项字段的比较指令的功能与条件分支或跳转指令相组合,以便保存条件码而不是将条件码设置为表示比较结果的值。 一个比较数是从存储位置或立即数字段中的任何一个获得的,而另一个比较数是从寄存器字段获得的。

    LOAD RELATIVE AND STORE RELATIVE FACILITY AND INSTRUCTIONS THEREFORE
    16.
    发明申请
    LOAD RELATIVE AND STORE RELATIVE FACILITY AND INSTRUCTIONS THEREFORE 审中-公开
    加载相关和存储相关设施及其说明

    公开(公告)号:WO2009087166A4

    公开(公告)日:2009-11-05

    申请号:PCT/EP2009050117

    申请日:2009-01-07

    Abstract: A method, system and program product for loading or storing memory data wherein the address of the memory operand is based an offset of the program counter rather than an explicitly defined address location. The offset is defined by an immediate field of the instruction which is sign extended and is aligned as a halfword address when added to the value of the program counter.

    Abstract translation: 一种用于加载或存储存储器数据的方法,系统和程序产品,其中存储器操作数的地址基于程序计数器的偏移而不是明确定义的地址位置。 偏移量由符号扩展的指令的立即字段定义,并在被添加到程序计数器的值时作为半字地址对齐。

    FINDING THE LENGTH OF A SET OF CHARACTER DATA HAVING A TERMINATION CHARACTER
    18.
    发明申请
    FINDING THE LENGTH OF A SET OF CHARACTER DATA HAVING A TERMINATION CHARACTER 审中-公开
    发现一组具有终止字符的字符数据的长度

    公开(公告)号:WO2013136214A1

    公开(公告)日:2013-09-19

    申请号:PCT/IB2013051647

    申请日:2013-03-01

    Applicant: IBM IBM UK

    CPC classification number: G06F9/30018 G06F9/30021 G06F9/30036 G06F9/30043

    Abstract: The length of character data having a termination character is determined. The character data for which the length is to be determined is loaded, in parallel, within one or more vector registers. An instruction is used that loads data in a vector register to a specified boundary, and provides a way to determine the number of characters loaded, using, for instance, another instruction. Further, an instruction is used to find the index of the first termination character, e.g., the first zero or null character. This instruction searches the data in parallel for the termination character. By using these instructions, the length of the character data is determined using only one branch instruction.

    Abstract translation: 确定具有终止字符的字符数据的长度。 要确定长度的字符数据并行加载到一个或多个向量寄存器中。 使用将向量寄存器中的数据加载到指定边界的指令,并且提供了使用例如另一个指令来确定加载的字符数的方法。 此外,使用指令来找到第一终止字符的索引,例如,第一个零或空字符。 该指令并行搜索终止字符的数据。 通过使用这些指令,仅使用一个分支指令来确定字符数据的长度。

    LOAD RELATIVE AND STORE RELATIVE FACILITY AND INSTRUCTIONS THEREFORE
    19.
    发明申请
    LOAD RELATIVE AND STORE RELATIVE FACILITY AND INSTRUCTIONS THEREFORE 审中-公开
    加载相对和存储相对设施及其说明

    公开(公告)号:WO2009087166A3

    公开(公告)日:2009-09-17

    申请号:PCT/EP2009050117

    申请日:2009-01-07

    Abstract: A method, system and program product for loading or storing memory data wherein the address of the memory operand is based an offset of the program counter rather than an explicitly defined address location. The offset is defined by an immediate field of the instruction which is sign extended and is aligned as a halfword address when added to the value of the program counter.

    Abstract translation: 一种用于加载或存储存储器数据的方法,系统和程序产品,其中存储器操作数的地址基于程序计数器的偏移而不是明确定义的地址位置。 偏移量由符号扩展的指令的立即字段定义,并在添加到程序计数器的值时作为半字地址对齐。

    COMPARE AND BRANCH FACILITY AND INSTRUCTION THEREFORE
    20.
    发明申请
    COMPARE AND BRANCH FACILITY AND INSTRUCTION THEREFORE 审中-公开
    比较和分支机构及其指导

    公开(公告)号:WO2009087158A3

    公开(公告)日:2009-09-17

    申请号:PCT/EP2009050105

    申请日:2009-01-07

    CPC classification number: G06F9/30058 G06F9/30094 G06F9/30167

    Abstract: An atomic compare and branch instruction is executed that combines the function of a compare instruction having an option field with a conditional branch or jump instruction such that condition codes are preserved rather than setting condition codes to a value representative of the compare results. One comparand is obtained from any one of a memory location or an immediate field and the other comparand is obtained from a register field.

    Abstract translation: 执行原子比较和分支指令,其将具有选项字段的比较指令的功能与条件分支或跳转指令相结合,使得保留条件代码而不是将条件代码设置为代表比较结果的值。 从存储器位置或立即场中的任何一个获得一个比较,并且从寄存器字段获得另一个比较。

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