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公开(公告)号：AU526203B2
公开(公告)日：1982-12-23
申请号：AU4868379
申请日：1979-07-05
Applicant: IBM
Inventor： VINAL ALBERT WATSON
IPC: H01L29/73 , G01R33/06 , H01L21/331 , H01L29/10 , H01L29/68 , H01L29/82 , H01L29/868 , H01L43/00 , H01L43/02 , H01L43/06 , H01L29/44
Abstract: A heretofore undiscovered suddenly conducting avalanche voltage effect is described with relationship to a new family of hybrid transistors. The devices constructed also exhibit magnetic sensitivity. The magnetic responsiveness of such devices creates a new family of magnetic sensors which utilize magnetic modulation of the avalanche voltage produced by the new effect. New transistor structure elements are incorporated in the devices. These include an impact ionization promoter means and an intrinsic, or high resistivity, depleted base region which extends at least partially from a collector toward an emitter. Minority carrier injection efficiency control means and transportation efficiency control means are also included. The character of the base region extending between the emissive junction and the collector is carefully controlled so that the product of the ionization current multiplication factor M and an electron-hole recombination probability factor alpha is less than unity. Within limits, any specifically desired avalanche voltage can be created by controlling the characteristics of the transistor structure. This voltage may then be varied bidirectionally by magnetic fields to form a new class of magnetic sensors.
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公开(公告)号：DE2727944A1
公开(公告)日：1978-01-05
申请号：DE2727944
申请日：1977-06-22
Applicant: IBM
Inventor： VINAL ALBERT WATSON
Abstract: HIGH CARRIER VELOCITY FET MAGNETIC SENSOR An FET structure for a magnetic field sensor which operates by achieving very high carrier velocities in the active region of the sensor is disclosed. A Hall output voltage is produced by the sensor in response to a magnetic flux field passing therethrough and, due to the high carrier velocities achieved, a very high sensitivity device is obtained by operating the FET structure in the pinch of mode or depletion mode. The position of the pinched off area of the conductive channel is varied to position the location of maximum carrier velocity in the channel at a desired point relative to an output probe. This position is controlled by the use of a control gate.
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公开(公告)号：GB1040022A
公开(公告)日：1966-08-24
申请号：GB2452163
申请日：1963-06-20
Applicant: IBM
Inventor： VINAL ALBERT WATSON
Abstract: 1,040,022. Magnetic storage devices. INTERNATIONAL BUSINESS MACHINES CORPORATION. June 20, 1963, No. 24521/63. Heading H3B. A storage matrix comprises magnetic elements each having a control aperture C and a read aperture R, the column energizing conductors being common to both the read and write apertures of respective columns of elements, and the row energizing conductors being separately associated with the control and read apertures in each row. A binary digit is written into or read from a magnetic element by applying the pulse trains (1)-(8), (1 1 )-(8 1 ) shown in Fig. 2 to respective conductors passing through the read aperture 11 and control aperture 12, Fig. 2 (a), which shows an element in the unblocked state. When alternate read pulses (1)-(4) are of significant magnitude and the control pulses (1 1 )-(4 1 ) are of lesser magnitude, the flux encircling the read aperture is reversed in direction, Figs. 2(b) to 2(e), and an output (1) 11 -(4) 11 is induced in a sense winding (not shown) threading aperture 11. An element is blocked when substantially the whole of its flux passes around both apertures as shown in Figs. 2 (f) to 2 (h), this condition being established by applying a significant negative control pulse (5 1 ) and a coincident read pulse (5) of lesser magnitude. When a core is blocked, read pulses of significant magnitude (6), (7) have negligible effect on the stable magnetic state and no output is produced. The element is unblocked into the state shown in Fig. 2(a) by the coincident application of a positive control pulse (8 1 ) of significant magnitude with a negative read pulse of lesser magnitude. The arrangement of matrix conductors in the various embodiments of a data store produce the significant pulses at the intersections of energized row and column conductors, and the pulses of lesser magnitude at all other apertures threaded by a single energized conductor. The lesser amplitude pulses act as biases which permit less critical current amplitudes to be used. Storage matrices. In Fig. 6, bipolar current sources 128, 129 are connected to respective conductors RX1, CY1 and RY2, CY2 which pass through all the reading and control apertures R, C of storage elements 101-104. Bipolar current sources for the other co-ordinate are connected to conductors RX1, CX2 and RX2, CX1, each threading control apertures in one column and read apertures in the other column. To read a single element a column and a row pulse source are rendered operative, the combined pulses in the read aperture of the selected element being sufficient to reverse the flux direction about that aperture. The adjacent element having its control aperture threaded by both energized conductors is unaffected as the currents act in opposite directions and mutually cancel. Similarly an element is blocked by applying pulses of appropriate polarity to a selected row and a column conductor. A modified circuit is shown in Fig. 7 in which separate pulse sources 130 1 , 130 11 and 1311, 131 11 are provided for the columns of read and control apertures. The Fig. 6 arrangement is applied to a larger matrix in Fig. 8 which shows the sense winding 140 and an inhibit winding 141, the latter winding being utilized in threeco-ordinate store applications. Each of the matrix conductors includes a characteristic impedance 180 only one of which is shown, this impedance being connected in parallel with the associated conductor between the pulse source and ground. A three co-ordinate matrix arrangement is shown in Fig. 9 in which a single element in each plane may be read or blocked simultaneously. Instead of separate magnetic elements a multi-aperture plate of ferrite 181 may be used, Fig. 11, the control and read apertures being positioned so as to prevent interference between the various magnetic circuits.
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公开(公告)号：DE1148589B
公开(公告)日：1963-05-16
申请号：DEI0016488
申请日：1959-05-26
Applicant: IBM DEUTSCHLAND
Inventor： VINAL ALBERT WATSON
IPC: H03K3/33
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公开(公告)号：DE3676520D1
公开(公告)日：1991-02-07
申请号：DE3676520
申请日：1986-02-05
Applicant: IBM
Inventor： VINAL ALBERT WATSON
Abstract: Disclosed is an improved method and apparatus for sensing magnetic reluctance variations. The invention may be used for magnetic ink character reading, such as is employed on bank checks, or for any of a variety of magnetic reluctance pickup applications. An improved magnetic reluctance sensor head (3) utilizes an essentially U or C-shaped magnetically permeable member (2) having a magnetizing coil encircling it. The coil is arranged to deliver essentially a constant magnetic flux to the U or C-shaped member. The tips of the U or C are placed adjacent to the element whose variation of reluctance is to be detected, e.g. a sheet of paper (12) having magnetic ink (13) deposited thereon, and a magneto resistive or other similar magnetic sensor is connected in the magnetic circuit either in parallel or in series with the variable reluctance which is to be sensed.
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Patent Agency Ranking
公开(公告)号：DE3378799D1
公开(公告)日：1989-02-02
申请号：DE3378799
申请日：1983-05-02
Applicant: IBM
Inventor： VINAL ALBERT WATSON
Abstract: The invention relates to an improved generic form of magnetic read head design for reading the vertical component of magnetization from a recorded magnetic medium, where data is written in the form of magnetic polarity reversals or transitions. It utilizes the principle of coupling of complementary magnetic poles from the medium to the sensor to improve the magnitude of magnetic field experienced by the sensor. Two coupling legs (1, 2) are arranged in vertical relationship to the recording medium. The legs are relatively widely spaced apart to have their ends proximate to complementary magnetic pole transitions on the medium for a given density of data (expressed as flux changes per inch). The other ends of the coupling legs are brought close together to direct the coupled field from the medium through a narrow gap in which a magnetic sensor is located. The coupling legs in the magnetic sensor are oriented relative to one another within this gap area so that the magnetic flux field passes through the most sensitive plane of the sensor
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公开(公告)号：AU4868379A
公开(公告)日：1980-01-17
申请号：AU4868379
申请日：1979-07-05
Applicant: IBM
Inventor： VINAL ALBERT WATSON
IPC: H01L29/73 , G01R33/06 , H01L21/331 , H01L29/10 , H01L29/68 , H01L29/82 , H01L29/868 , H01L43/00 , H01L43/02 , H01L43/06 , H01L29/44
Abstract: A heretofore undiscovered suddenly conducting avalanche voltage effect is described with relationship to a new family of hybrid transistors. The devices constructed also exhibit magnetic sensitivity. The magnetic responsiveness of such devices creates a new family of magnetic sensors which utilize magnetic modulation of the avalanche voltage produced by the new effect. New transistor structure elements are incorporated in the devices. These include an impact ionization promoter means and an intrinsic, or high resistivity, depleted base region which extends at least partially from a collector toward an emitter. Minority carrier injection efficiency control means and transportation efficiency control means are also included. The character of the base region extending between the emissive junction and the collector is carefully controlled so that the product of the ionization current multiplication factor M and an electron-hole recombination probability factor alpha is less than unity. Within limits, any specifically desired avalanche voltage can be created by controlling the characteristics of the transistor structure. This voltage may then be varied bidirectionally by magnetic fields to form a new class of magnetic sensors.
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公开(公告)号：DE2645460A1
公开(公告)日：1977-05-12
申请号：DE2645460
申请日：1976-10-08
Applicant: IBM
Inventor： VINAL ALBERT WATSON
Abstract: 1522895 Decoding digital data signals INTERNATIONAL BUSINESS MACHINES CORP 31 Aug 1976 [29 Oct 1975] 36049/76 Headings G4C and G4M A decoding method of, and apparatus for use in decoding a generalized self-clocking data stream is described. The data stream may consist of electrical pulses from a communications line or be derived by magnetic or optical scanning of a recording medium. The self-clocking code employed may be F2F, S2S, SKS, phase-shift or delta-distance codes. In each of the codes data events (positive transitions) and control events (negative transitions) are interleaved on a one-for-one basis; corresponding to this, "bars" (positive data) and "spaces" (negative data) are also interleaved on a one-for-one basis. If, as in all the self-clocking codes mentioned, there exists a minimum bar or space width, and P possible bar or space widths greater than the minimum (P being 1 in most cases), it is shown that a bar-space or space-bar pair can have 2P + 1 possible widths. Based upon these 2P + 1 possibilities, and on a reference width supplied directly to a decoder apparatus or obtained by scanning a bar-space or a space-bar pair in a preamble stream, search gates are then erected in the data steam at the possible pulse positions and, depending upon the actual pulse positions, the data content of the data stream is obtained. Formulae are given for the positions of the various search gates and for velocity and acceleration corrections thereof. The reference width may be resealed for use in each succeeding cell (containing one data event and one control event). In Figs. 10A, 10B, 10C, counters 3, 4 and 5 count clock pulses from a source 1 at different rates. The reference width is obtained from a preamble stream and stored at 16. Counters 3, 4 and 5 count up to their various maximum counts (all equal) at various times and if, at a particular time, an X (data) signal occurs in a search gate, the contents of the appropriate counter are fed to the store 16 to overwrite its present contents. A counter 18 counts down from the contents of the store 16 to zero, each counting down of the counter 18 to zero representing a subdivision of a cell. Following each such counting down to zero of the counter 18, it is recharged from the store 18 and counting down to zero again proceeds. A shift register 23 stores a sequence of zeroes representing the number of times the counter 18 has counted down to zero, and logic circuitry 25-32 determines in which subdivision of the cell a data signal occurs. Following each such detection of a data signal, the store 16 is loaded with the current contents of the appropriate counter 3, 4 or 5 as an updated reference width, this providing an inbuilt velocity correction. A circuit identical to that of Figs. 10A, 10B, 10C is provided for the control (Y) signals, the subdivisions of the cells for data signals and control signals being determined and transmitted to a logic matrix, Fig. 13A (not shown) to decode the data signals. An error signal is generated if no data or control signals are detected in any given cell. In the previous embodiment separate circuitry is provided for the data signals and the control signals, search gates for each being erected relative to the preceding like signals; in a modification, Figs. 16, 17 (not shown) each search gate is erected relative to the preceding signal (of either type), and common circuitry for the data signals and the control signals is employed.
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