公开(公告)号：JP2005197734A

公开(公告)日：2005-07-21

申请号：JP2005000206

申请日：2005-01-04

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BEDELL STEVEN W ,  DORIS BRUCE B ,  ZHANG YING ,  ZHU HUILONG

IPC: H01L21/20 ,  H01L21/336 ,  H01L29/76 ,  H01L29/78 ,  H01L29/786 ,  H01L29/94 ,  H01L31/062

CPC classification number: H01L29/785 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/78687

Abstract: PROBLEM TO BE SOLVED: To provide a method and a device, realizing a strained Si film with reduced number of defects.
SOLUTION: The strained Si film is formed by selectively growing a fin arranged in a perpendicular direction to the surface of a non-conductive substrate or Si on the side face of a relaxed SiGe block. Next, a dielectric gate comprising an oxide or a high k material or a combination thereof, for example, can be formed on the surface of the strained Si film. Further, by removing the relaxed SiGe block without substantially influencing the stress of the strained Si film, a second gate oxide can be formed on the surface previously occupied by the relaxed SiGe block. Thus, a MOSFET and a finFET of a single gate, double gate, or more gates can be formed, with the semiconductor device having the strained Si fin arranged in the perpendicular direction on the non-conductive substrate, with a channel having reduced number of defects or reduced dimension or both.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：为了提供一种方法和装置，实现了具有减少的缺陷数量的应变Si膜。 解决方案：通过选择性地生长沿垂直于非导电衬底的表面布置的翅片或在弛豫的SiGe块的侧面上的Si来形成应变Si膜。 接下来，可以在应变Si膜的表面上形成例如包含氧化物或高k材料或其组合的电介质栅。 此外，通过去除弛豫的SiGe块而基本上不影响应变的Si膜的应力，可以在松弛的SiGe块以前占据的表面上形成第二栅极氧化物。 因此，可以形成单栅极，双栅极或更多栅极的MOSFET和finFET，其中半导体器件具有沿非垂直方向布置在非导电衬底上的应变Si鳍，沟道具有减少的数量 缺陷或尺寸减小或两者兼有。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2010206185A

公开(公告)日：2010-09-16

申请号：JP2010016896

申请日：2010-01-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： LUO ZHIJIONG ,  ZHU HUILONG ,  KIM SEONG-DONG

IPC: H01L29/786 ,  H01L21/265 ,  H01L21/336

CPC classification number: H01L21/26586 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7848

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device having asymmetric p/n junctions.
SOLUTION: The semiconductor device includes an embedded insulator layer formed on a bulk substrate; a first type semiconductor material formed on the embedded insulator layer and corresponding to a body region of a field-effect transistor (FET); a second type semiconductor material, formed over the embedded insulator layer so as to be adjacent to the mutually opposing sides of the body region, corresponding to source and drain regions of the FET device, and having a bandgap which differs from that of the first type semiconductor material, wherein a source-side p/n junction of the FET is located mostly within either the first or the second type of semiconductor materials having a narrower bandgap; and a drain-side p/n junction of the FET is located within either the first or the second type semiconductor materials which have a wider bandgap.
COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供具有不对称p / n结的半导体器件。 解决方案：半导体器件包括形成在本体衬底上的嵌入式绝缘体层; 形成在所述嵌入绝缘体层上并对应于场效应晶体管（FET）的体区的第一类型半导体材料; 第二类型半导体材料，其形成在所述嵌入式绝缘体层上以与所述FET器件的源极和漏极区域相对应的与所述体区域的相对的相对侧相邻并且具有与所述第一类型的不同的带隙 半导体材料，其中FET的源极p / n结大部分位于具有较窄带隙的第一或第二类型的半导体材料之中; 并且FET的漏极侧p / n结位于具有更宽带隙的第一或第二类型半导体材料中。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2007158329A

公开(公告)日：2007-06-21

申请号：JP2006317780

申请日：2006-11-24

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ZHU HUILONG ,  LUO ZHIJIONG

IPC: H01L29/786 ,  H01L21/28 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/7842

Abstract: PROBLEM TO BE SOLVED: To provide a finFET structure with enhanced performance and a method of producing the finFET structure.
SOLUTION: A semiconductor structure and its producing method include a semiconductor fin located on a substrate. A gate electrode is located over the semiconductor fin. The gate electrode has a first stress in a first region located closer to the semiconductor fin and a second stress which is different from the first stress in a second region located farther from the semiconductor fin. The semiconductor fin may also be positioned so that it is placed on a pedestal within the substrate. The semiconductor structure is annealed under desirable stress conditions to enhance the performance of the semiconductor device.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供具有增强性能的finFET结构和制造finFET结构的方法。 解决方案：半导体结构及其制造方法包括位于基板上的半导体翅片。 栅电极位于半导体鳍上方。 栅电极在位于更靠近半导体鳍片的第一区域中具有第一应力，并且在远离半导体鳍片的第二区域中具有与第一应力不同的第二应力。 半导体鳍片也可以被定位成使得它被放置在衬底内的基座上。 半导体结构在期望的应力条件下退火以提高半导体器件的性能。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2007150319A

公开(公告)日：2007-06-14

申请号：JP2006319296

申请日：2006-11-27

Applicant: Chartered Semiconductor Mfg Ltd ,  Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation ,  チャータード・セミコンダクター・マニュファクチャリング・リミテッド

Inventor： LUO ZHIJIONG ,  ZHU HUILONG ,  CHONG YUNG FU

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L21/823814 ,  H01L21/823807 ,  H01L21/823835 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/4975 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a field effect transistor (FET).
SOLUTION: This method includes a step of forming a gate structure on a semiconductor substrate, and a step of forming a recess in the substrate to embed a second semiconductor material in the recess. The gate structure includes a gate dielectric layer, a conductive layer and an insulation layer. The formation of the gate structure includes a step of recessing a conductive layer in the gate structure, and the step of recessing the conductive layer and the step of forming the recess in the substrate are executed in a single step. An FET device is also provided.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种制造场效应晶体管（FET）的方法。 解决方案：该方法包括在半导体衬底上形成栅极结构的步骤，以及在衬底中形成凹陷以将第二半导体材料嵌入凹槽中的步骤。 栅极结构包括栅极电介质层，导电层和绝缘层。 栅极结构的形成包括使栅极结构中的导电层凹陷的步骤，并且在单个步骤中执行使导电层凹陷的步骤和在衬底中形成凹部的步骤。 还提供了FET器件。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2007123880A

公开(公告)日：2007-05-17

申请号：JP2006286977

申请日：2006-10-20

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ZHU HUILONG ,  CHENG KANGGUO

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/786

CPC classification number: H01L21/26506 ,  H01L21/26586 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a field effect transistor (FET) including a source side semiconductor, a drain side semiconductor, and a gate.
SOLUTION: The source side semiconductor is made of a high-mobility semiconductor material, and the drain side semiconductor is made of a low-leakage semiconductor material. According to one embodiment, the FET is a metal-oxide-semiconductor field effect transistor (MOSFET). A method for manufacturing the FET is also provided.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种包括源极半导体，漏极侧半导体和栅极的场效应晶体管（FET）。 解决方案：源极半导体由高迁移率半导体材料制成，漏极侧半导体由低泄漏半导体材料制成。 根据一个实施例，FET是金属氧化物半导体场效应晶体管（MOSFET）。 还提供了一种用于制造FET的方法。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2006019727A

公开(公告)日：2006-01-19

申请号：JP2005183624

申请日：2005-06-23

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ZHU HUILONG

IPC: H01L21/336 ,  H01L21/00 ,  H01L21/22 ,  H01L21/225 ,  H01L21/762 ,  H01L29/10 ,  H01L29/78 ,  H01L29/786 ,  H01L31/072

CPC classification number: H01L21/2255 ,  H01L21/22 ,  H01L21/7624 ,  H01L29/1045 ,  H01L29/66492 ,  H01L29/66628 ,  H01L29/66742 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/78618 ,  H01L29/78684

Abstract: PROBLEM TO BE SOLVED: To provide a P-type MOSFET structure having strained silicon, and to provide its manufacturing method.
SOLUTION: The P-type MOSFET seals a gate 110 with an insulating material, forms a germanium-containing layer outside a sidewall 105, then diffuses germanium into a silicon layer or bulk silicon on an insulator through annealing or oxidization, and thus forms a slanted, built-in source/drain 40 of silicon-germanium and/or an extension section (geSiGe-SDE). In an SOI device, the geSiGe-SDE generates a horizontal (parallel to the plane of the gate's dielectric) pressure stress and a vertical (perpendicular to the plane of the gate's dielectric) tensile stress in a PMOSFET channel, thereby forming a structure that will make the PMOSFET performance improved.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供具有应变硅的P型MOSFET结构，并提供其制造方法。 解决方案：P型MOSFET用绝缘材料密封栅极110，在侧壁105外形成含锗层，然后通过退火或氧化将锗扩散到绝缘体上的硅层或体硅中，因此 形成硅 - 锗和/或延伸部分（geSiGe-SDE）的倾斜的内置源极/漏极40。 在SOI器件中，GeSiGe-SDE在PMOSFET通道中产生水平（平行于栅极电介质的平面）压力应力和垂直（垂直于栅极电介质的平面）拉伸应力，由此形成将 使PMOSFET性能提高。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：WO2007082199A3

公开(公告)日：2007-11-29

申请号：PCT/US2007060265

申请日：2007-01-09

Applicant: IBM ,  ZHU HUILONG

Inventor： ZHU HUILONG

IPC: H01L23/48

CPC classification number: H01L21/28052 ,  H01L21/76889 ,  H01L21/76895 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/78 ,  H01L2924/0002 ,  Y10S257/90 ,  Y10S257/92 ,  H01L2924/00

Abstract: Embodiments herein present a structure, method, etc. for making high density MOSFET circuits with different height contact lines. The MOSFET circuits comprise a contact line (500, 1300), a gate (310, 1210) situated proximate the contact line (500, 1300). The contact line (500, 1300) comprises a height that is less than the height of the gate (310, 1210). The MOSFET circuits further comprise gate spacers (710, 715, 1610, 1615) situated proximate the gate (310, 1210) and no contact line spacer situated proximate the contact line (500, 1300) and between the contact line (500, 1300) and the gate (310, 1210).

Abstract translation: 本文的实施例呈现用于制造具有不同高度接触线的高密度MOSFET电路的结构，方法等。 MOSFET电路包括接触线（500,1300），位于接触线（500,1300）附近的栅极（310,1210）。 接触线（500,1300）包括小于浇口（310,1210）的高度的高度。 MOSFET电路进一步包括位于栅极（310,1210）附近并且不位于接触线（500,1300）附近和接触线（500,1300）之间的接触线间隔件的栅极间隔件（710,715,1610,1615） 和门（310,1210）。

公开(公告)号：WO2006063060A3

公开(公告)日：2006-11-16

申请号：PCT/US2005044281

申请日：2005-12-08

Applicant: IBM ,  CHIDAMBARRAO DURESETI ,  LI YING ,  MALIK RAJEEV ,  NARASIMHA SHREESH ,  YANG HAINING ,  ZHU HUILONG

Inventor： CHIDAMBARRAO DURESETI ,  LI YING ,  MALIK RAJEEV ,  NARASIMHA SHREESH ,  YANG HAINING ,  ZHU HUILONG

IPC: H01L21/31 ,  H01L23/58

CPC classification number: H01L29/7843 ,  H01L21/823807 ,  H01L29/66772 ,  Y10S438/938

Abstract: The present invention provides a semiconductor device having dual nitride liners, which provide an increased transverse stress state for at least one FET (300) and methods for the manufacture of such a device. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device comprising the steps of applying a first silicon nitride liner (360) to the device and applying a second silicon nitride liner (370) adjacent the fast silicon nitride liner, wherein at least one of the first and second silicon nitride liners induces a transverse stress in a silicon channel (330) beneath at least one of the first and second silicon nitride liner.

Abstract translation: 本发明提供一种具有双重氮化物衬垫的半导体器件，其为至少一个FET（300）提供增加的横向应力状态以及用于制造这种器件的方法。 本发明的第一方面提供了一种用于制造半导体器件的方法，包括以下步骤：将第一氮化硅衬垫（360）施加到器件上，并施加与快速氮化硅衬垫相邻的第二氮化硅衬垫（370） ，其中所述第一和第二氮化硅衬垫中的至少一个在所述第一和第二氮化硅衬垫中的至少一个下方的硅沟道（330）中引起横向应力。

公开(公告)号：JP2011124601A

公开(公告)日：2011-06-23

申请号：JP2011024165

申请日：2011-02-07

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ZHU HUILONG ,  YANG DAEWON

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/786

CPC classification number: H01L21/31116 ,  H01L21/823807 ,  H01L21/823864 ,  H01L21/823871 ,  H01L29/7843

Abstract: PROBLEM TO BE SOLVED: To provide a structure and method for providing mechanical stress into a CMOS structure for raising device performance and improving the yield of a chip. SOLUTION: A CMOS structure and methods for fabricating the CMOS structure are provided, wherein a first stressed layer located over a first transistor and a second stressed layer located over a second transistor abut but do not overlap. Such an abutment absent overlap provides for enhanced manufacturing flexibility when forming a contact to a silicide layer upon a source/drain region within one of the first transistor and the second transistor. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供一种将机械应力提供到CMOS结构中以提高器件性能并提高芯片产量的结构和方法。 提供了CMOS结构和制造CMOS结构的方法，其中位于第一晶体管之上的第一应力层和位于第二晶体管上方的第二应力层邻接但不重叠。 当在第一晶体管和第二晶体管之一内的源极/漏极区域上形成与硅化物层的接触时，这种不存在重叠的基台提供增强的制造灵活性。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2011018904A

公开(公告)日：2011-01-27

申请号：JP2010151970

申请日：2010-07-02

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： LUO ZHIJIONG ,  ZHU HUILONG ,  LIANG QINGQING ,  YIN HAIZHOU

IPC: H01L29/786 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092 ,  H01L29/41 ,  H01L29/417

CPC classification number: H01L21/84 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L27/1203 ,  H01L29/7843 ,  H01L29/7848

Abstract: PROBLEM TO BE SOLVED: To provide a complementary metal-oxide film semiconductor (CMOS) device that is free from causing troubles in contact formation by a stress liner, and to provide a method of manufacturing the device.SOLUTION: The complementary metal-oxide film semiconductor (CMOS) device is prepared with a constitution having a silicon-dioxide layer 102 on a silicon-substrate layer, and a concave source/drain trench. A nitride stress liner 104 is deposited in the concave source/drain trench, and further an oxide layer 106 is deposited thereon. The CMOS device is set on a handling wafer, the silicon-substrate layer is removed, and the silicon-dioxide layer 102 is etched to form an opening in contact with part of a source/drain region 170. Resultantly, a contact 180 is formed.

Abstract translation: 要解决的问题：提供一种互补的金属氧化物半导体（CMOS）器件，其不会引起应力衬垫的接触形成的麻烦，并且提供一种制造器件的方法。解决方案：互补金属氧化物膜 半导体（CMOS）器件通过在硅衬底层上具有二氧化硅层102和凹入的源/漏沟槽的结构来制备。 氮化物应力衬垫104沉积在凹形源/漏沟槽中，并且另外在其上沉积氧化物层106。 将CMOS器件设置在处理晶片上，去除硅衬底层，并且蚀刻二氧化硅层102以形成与源极/漏极区域170的一部分接触的开口。结果，形成接触件180 。