公开(公告)号：WO2006060574A3

公开(公告)日：2006-07-20

申请号：PCT/US2005043473

申请日：2005-12-01

Applicant: IBM ,  FANG SUNFEI ,  CABRAL CYRIL JR ,  DZIOBKOWSKI CHESTER T ,  LAVOIE CHRISTIAN ,  WANN CLEMENT H

Inventor： FANG SUNFEI ,  CABRAL CYRIL JR ,  DZIOBKOWSKI CHESTER T ,  LAVOIE CHRISTIAN ,  WANN CLEMENT H

IPC: H01L21/8238

CPC classification number: H01L21/823835

Abstract: A method of forming a dual self-aligned fully silicided gate in a CMOS device requiring only one lithography level, wherein the method comprises forming a first type semiconductor device (270) having a first well region (253) in a semiconductor substrate (252), first source/drain silicide areas (266) in the first well region (253), and a first type gate (263) isolated from the first source/drain silicide areas (266); forming a second type semiconductor device (280) having a second well region (254) in the semiconductor substrate (252), second source/drain silicide areas (256) in the second well region (254), and a second type gate (258) isolated from the second source/drain silicide areas (256); selectively forming a first metal layer (218) over the second type semiconductor device (280); performing a first fully silicided (FUSI) gate formation on only the second type gate (258); depositing a second metal layer (275) over the first and second type semiconductor devices (270,280); and performing a second FUSI gate formation on only the first type gate (263).

Abstract translation: 一种在仅需要一个光刻级别的CMOS器件中形成双自对准全硅化栅极的方法，其中该方法包括在半导体衬底（252）中形成具有第一阱区（253）的第一类型半导体器件（270） ，第一阱区（253）中的第一源极/漏极硅化物区域（266）以及与第一源极/漏极硅化物区域（266）隔离的第一类型栅极（263）; 形成具有半导体衬底（252）中的第二阱区（254），第二阱区（254）中的第二源极/漏极硅化物区（256）和第二类型栅极（258）的第二类型半导体器件 ）与第二源极/漏极硅化物区域（256）隔离; 在所述第二类型半导体器件（280）上方选择性地形成第一金属层（218）; 仅在所述第二类型栅极（258）上执行第一全硅化物（FUSI）栅极形成; 在第一和第二类型半导体器件（270,280）上沉积第二金属层（275）; 以及仅在第一类型栅极（263）上执行第二FUSI栅极形成。

公开(公告)号：JP2007329474A

公开(公告)日：2007-12-20

申请号：JP2007135089

申请日：2007-05-22

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DYER THOMAS W ,  FANG SUNFEI ,  HOLT JUDSON R

IPC: H01L21/8238 ,  H01L21/20 ,  H01L21/336 ,  H01L21/8244 ,  H01L27/092 ,  H01L27/11 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/045 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823857 ,  H01L29/1037 ,  H01L29/78 ,  H01L29/7853

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor substrate having different surface orientations (namely, hybrid surface orientation).
SOLUTION: In the semiconductor substrate, a first device area 2 has a substantially flat surface 16A which is oriented to one orientation of group of first equivalent crystal surfaces, and a second device area contains a protrusive semiconductor structure 18 having a plurality of cross surfaces 16B which are oriented to an orientation of group of other equivalent crystal surfaces. A semiconductor device structure can be formed using such a semiconductor substrate. Particularly, a first field-effect transistor (FET) can be formed in the first device area, the first FET contains a channel which is located along a substantially flat surface in the first device area. A second complementary FET can be formed in the second device area, and the second complementary FET contains a channel which is located along the plurality of cross surfaces of the protrusive semiconductor structure in the second device area.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供具有不同表面取向（即混合表面取向）的半导体衬底。 解决方案：在半导体衬底中，第一器件区域2具有基本上平坦的表面16A，其被定向为第一等效晶体表面的一组取向，并且第二器件区域包含突出半导体结构18，突出半导体结构18具有多个 横向表面16B被定向成其他等效晶体表面的组的取向。 可以使用这种半导体衬底形成半导体器件结构。 特别地，第一场效应晶体管（FET）可以形成在第一器件区域中，第一FET包含沿着第一器件区域中的基本上平坦的表面定位的沟道。 第二互补FET可以形成在第二器件区域中，并且第二互补FET包含沿着第二器件区域中的突出半导体结构的多个十字表面定位的沟道。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007134718A

公开(公告)日：2007-05-31

申请号：JP2006303401

申请日：2006-11-08

Applicant: Chartered Semiconductor Mfg Ltd ,  Internatl Business Mach Corp ,  Samsung Electronics Co Ltd ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation ,  サムスン エレクトロニクス カンパニー リミテッド ,  チャータード・セミコンダクター・マニュファクチャリング・リミテッド

Inventor： FANG SUNFEI ,  KIM JUN JUNG ,  LUO ZHIJIONG ,  NG HUNG Y ,  ROVEDO NIVO ,  TEH YOUNG WAY

IPC: H01L21/8238 ,  C23C16/34 ,  H01L21/318 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L21/823864 ,  H01L21/823807

Abstract: PROBLEM TO BE SOLVED: To provide a SMT (stress memory technique) for both of an nFET and a pFET.
SOLUTION: The method includes forming a tensile stress layer 120 over the nFET 104 and a compressive stress layer 122 over the pFET 106, annealing 150 to memorize stress in the semiconductor device and removing the stress layers. The compressive stress layer 122 may include a high stress silicon nitride deposited using a high density plasma (HDP) deposition method. The annealing step may include the one used in a temperature of approximately 400-1,200°C. The high stress compressive silicon nitride and/or the anneal temperatures ensure that the compressive stress memorization is retained in the pFET 106.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：为nFET和pFET两者提供SMT（应力记忆技术）。 解决方案：该方法包括在nFET104上形成拉伸应力层120，在pFET 106上形成压应力层122，退火150以将应力记忆在半导体器件中并除去应力层。 压应力层122可以包括使用高密度等离子体（HDP）沉积方法沉积的高应力氮化硅。 退火步骤可以包括在约400-1200℃的温度下使用的退火步骤。 高应力压缩氮化硅和/或退火温度确保压应力记忆保留在pFET 106中。版权所有：（C）2007，JPO＆INPIT

公开(公告)号：WO2007016514A3

公开(公告)日：2007-04-05

申请号：PCT/US2006029800

申请日：2006-08-01

Applicant: IBM ,  NAYFEH HASAN M ,  KUMAR MAHENDER ,  FANG SUNFEI ,  KEDZIERSKI JAKUB T ,  CABRAL CYRIL JR

Inventor： NAYFEH HASAN M ,  KUMAR MAHENDER ,  FANG SUNFEI ,  KEDZIERSKI JAKUB T ,  CABRAL CYRIL JR

IPC: H01L21/8238 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/8234 ,  H01L29/00

CPC classification number: H01L21/823835 ,  H01L21/823842 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

Abstract: A MOSFET structure and method of forming is described. The method includes forming a metal-containing layer (56) that is thick enough to fully convert the semiconductor layer (22) to a semiconductor metal alloy in a first MOSFET type region (40) but only thick enough to partially convert the semiconductor layer (20) to a semiconductor metal alloy in a second MOSFET type region (30). In one embodiment, the gate stack in a first MOSFET region (40) is recessed prior to forming the metal-containing layer (56) so that the height of the first MOSFET semiconductor stack is less than the height of the second MOSFET semiconductor stack. In another embodiment, the metal-containing layer (56) is thinned over a first type MOSFET region (40) relative to a second type MOSFET region (30) prior to the conversion process.

Abstract translation: 描述了MOSFET结构和形成方法。 该方法包括形成足够厚的含金属层（56），以将半导体层（22）完全转换为第一MOSFET型区域（40）中的半导体金属合金，但仅足够厚以部分地转换半导体层（ 20）连接到第二MOSFET型区域（30）中的半导体金属合金。 在一个实施例中，在形成含金属层（56）之前，第一MOSFET区域（40）中的栅极堆叠是凹进的，使得第一MOSFET半导体堆叠的高度小于第二MOSFET半导体堆叠的高度。 在另一个实施例中，在转换过程之前，相对于第二类型MOSFET区域（30），含金属层（56）在第一类型MOSFET区域（40）上变薄。

公开(公告)号：WO2006060575A2

公开(公告)日：2006-06-08

申请号：PCT/US2005043474

申请日：2005-12-01

Applicant: IBM ,  CABRAL CYRIL JR ,  DZIOBKOWSKI CHESTER T ,  ELLIS-MONAGHAN JOHN J ,  FANG SUNFEI ,  LAVOIE CHRISTIAN ,  LUO ZHIJIONG ,  NAKOS JAMES S ,  STEEGEN AN L ,  WANN CLEMENT H

Inventor： CABRAL CYRIL JR ,  DZIOBKOWSKI CHESTER T ,  ELLIS-MONAGHAN JOHN J ,  FANG SUNFEI ,  LAVOIE CHRISTIAN ,  LUO ZHIJIONG ,  NAKOS JAMES S ,  STEEGEN AN L ,  WANN CLEMENT H

IPC: H01L21/8238 ,  H01L21/3205 ,  H01L21/44

CPC classification number: H01L21/28518 ,  H01L21/823814 ,  H01L21/823835

Abstract: A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region (103) in a semiconductor substrate (102) for accommodation of a first type semiconductor device (130); forming a second well region (104) in the semiconductor substrate (102) for accommodation of a second type semiconductor device (140); shielding the first type semiconductor device (130) with a mask (114); depositing a first metal layer (118) over the second type semiconductor device (140); performing a first salicide formation on the second type semiconductor device (140); removing the mask (114); depositing a second metal layer (123) over the first and second type semiconductor devices (130,140); and performing a second salicide formation on the first type semiconductor device (130). The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different suicide material over different devices.

Abstract translation: 一种制造互补金属氧化物半导体（CMOS）器件的方法，其中所述方法包括在半导体衬底（102）中形成用于容纳第一类型半导体器件（130）的第一阱区（103）; 在所述半导体衬底（102）中形成用于容纳第二类型半导体器件（140）的第二阱区（104）; 用掩模（114）屏蔽所述第一类型半导体器件（130）; 在所述第二类型半导体器件（140）上沉积第一金属层（118）; 在所述第二类型半导体器件（140）上执行第一自对准硅化物形成; 去除所述面罩（114）; 在第一和第二类型半导体器件（130,140）上沉积第二金属层（123）; 以及在所述第一类型半导体器件（130）上执行第二自对准硅化物形成。 该方法仅需要一个图案级别，并且消除图案覆盖，因为它也简化了在不同设备上形成不同的自杀材料的过程。

公开(公告)号：SG132607A1

公开(公告)日：2007-06-28

申请号：SG2006077119

申请日：2006-11-08

Applicant: IBM ,  CHARTERED SEMICONDUCTOR MFG ,  SAMSUNG ELECTRONICS CO LTD

Inventor： FANG SUNFEI ,  KIM JUN JUNG ,  LUO ZHIJIONG ,  NG HUNG Y ,  ROVEDO NIVO ,  TEH YOUNG WAY

Abstract: A method for providing a dual stress memory technique in a semiconductor device (100) including an nFET (104, 204) and a pFET (106, 206) and a related structure are disclosed. One embodiment of the method includes forming a tensile stress layer (120) over the nFET (104) and a compressive stress layer (122) over the pFET (106), annealing to memorize stress in the semiconductor device and removing the stress layers. The compressive stress layer may include a high stress silicon nitride deposited using a high density plasma (HDP) deposition method. The annealing step may include using a temperature of approximately 400-1200 [err]C. The high stress compressive silicon nitride and/or the anneal temperatures ensure that the compressive stress memorization is retained in the pFET.