公开(公告)号：US10249567B2

公开(公告)日：2019-04-02

申请号：US15853853

申请日：2017-12-25

Applicant: Industrial Technology Research Institute ,  Intellectual Property Innovation Corporation

Inventor： Jie-Mo Lin ,  Shu-Wei Kuo ,  Wei-Yuan Cheng ,  Chen-Tsai Yang

IPC: H01L23/528 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498

Abstract: A redistribution layer structure of the semiconductor package includes a dielectric layer having a thickness, at least one upper conductive wire disposed on a first surface of the dielectric layer, at least one lower conductive wire disposed on a second surface of the dielectric layer, and vias penetrating the dielectric layer and connecting the at least one upper conductive wire and the at least one lower conductive wire. Each via has a cross-section at one upper conductive wire. The cross-section has a third width. The ratio of the third width to the thickness of the dielectric layer is less than or equal to 1. The ratio of the pitch between every two adjacent vias to the third width is greater than or equal to 0.5.

公开(公告)号：US10950588B2

公开(公告)日：2021-03-16

申请号：US16027374

申请日：2018-07-05

Applicant: Industrial Technology Research Institute

Inventor： Cheng-Hung Yu ,  Tai-Jui Wang ,  Chieh-Wei Feng ,  Wei-Yuan Cheng

IPC: H01L25/16 ,  H01L23/31 ,  H01L23/538 ,  H01L23/60 ,  H01L23/00 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L29/786

Abstract: A chip package structure including a redistribution structure layer, at least one chip, and an encapsulant is provided. The redistribution structure layer includes at least one redistribution circuit, at least one transistor electrically connected to the redistribution circuit, and a plurality of conductive vias electrically connected to the redistribution circuit and the transistor. The chip is disposed on the redistribution structure layer and electrically connected to the redistribution structure layer. The encapsulant is disposed on the redistribution structure layer and at least encapsulates the chip. A manufacturing method of a chip package structure is also provided.

公开(公告)号：US10709956B1

公开(公告)日：2020-07-14

申请号：US16354163

申请日：2019-03-14

Applicant: Industrial Technology Research Institute

Inventor： Min-Hsiung Liang ,  Yen-Ting Wu ,  Wei-Yuan Cheng ,  Ming-Huan Yang

IPC: A63F9/00 ,  A63B71/06

Abstract: A multiplayer sports formation arrangement prompting method adapted to monitor, by a computing device, a formation of a plurality of athletes participating in a multiplayer sport to prompt each of the athletes to adjust a position is provided, in which at least two wind sensors and a positioning device are disposed on or around each of the athletes. In this method, relative positions of the athletes with respect to each other are detected by using the positioning device, a wind direction is detected by using the at least two wind sensors disposed on or around a first athlete of the athletes, a second athlete behind the first athlete is prompted to adjust the position to enter a low wind resistance zone according to the relative position of the first athlete with respect to the second athlete and the detected wind direction, and the second athlete is prompted to adjust a position within the low wind resistance zone based on values detected by the at least two wind sensors disposed on or around the second athlete.

公开(公告)号：US10461035B2

公开(公告)日：2019-10-29

申请号：US15849593

申请日：2017-12-20

Applicant: Industrial Technology Research Institute ,  Intellectual Property Innovation Corporation

Inventor： Shu-Wei Kuo ,  Wei-Yuan Cheng ,  Chen-Tsai Yang ,  Jie-Mo Lin

IPC: H01L23/538 ,  H01L23/14 ,  H01L23/15 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498

Abstract: A semiconductor package structure includes a redistribution structure, a chip, an upper dielectric layer, a plurality of conductive members and an encapsulation layer. The redistribution structure includes a redistribution layer and a first dielectric layer disposed on the redistribution layer. The upper dielectric layer is disposed between the chip and the first dielectric layer of the redistribution structure, wherein the upper dielectric layer and the first dielectric layer are organic materials. A plurality of conductive members is disposed between the redistribution layer and the chip. Each conductive member has a first end adjacent to the chip and a second end adjacent to the redistribution structure, wherein the first end of said each conductive member contacts with the upper dielectric layer and the second end of said each conductive member contacts with the first dielectric layer.

公开(公告)号：US20220130744A1

公开(公告)日：2022-04-28

申请号：US17159012

申请日：2021-01-26

Applicant: Industrial Technology Research Institute

Inventor： Shu-Wei Kuo ,  Chen-Tsai Yang ,  Wei-Yuan Cheng ,  Chien-Hsun Chu ,  Shau-Fei Cheng

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48

Abstract: Provided is a forming method of a redistribution structure including: forming a first redistribution layer and a first compensation circuit layer on a substrate, wherein the first compensation circuit layer surrounds the first redistribution layer, and the first compensation circuit layer and the first redistribution layer are electrically insulated from each other; forming a first dielectric layer on the first redistribution layer and the first compensation circuit layer; and forming a second redistribution layer and a second compensation circuit layer on the first dielectric layer, wherein the second compensation circuit layer surrounds the second redistribution layer, the second compensation circuit layer and the second redistribution layer are electrically insulated from each other, the second compensation circuit layer is connected to the first compensation circuit layer, and the second redistribution layer is connected to the first redistribution layer.

公开(公告)号：US20200185344A1

公开(公告)日：2020-06-11

申请号：US16459639

申请日：2019-07-02

Applicant: Industrial Technology Research Institute

Inventor： Wei-Yuan Cheng ,  Chen-Tsai Yang

IPC: H01L23/00 ,  H01L27/02 ,  H01L23/31

Abstract: A chip package structure includes a redistribution circuit layer, at least one chip and an encapsulation material. The redistribution circuit layer includes at least one transistor. The chip is arranged on the redistribution circuit layer and is electrically connected to the redistribution circuit layer. The encapsulation material is arranged on the redistribution circuit layer and covers the at least one chip. When the chip package structure includes one or more chips, a position of the chip is taken as a reference for arrangement of a position of the at least one transistor.

公开(公告)号：US20190131271A1

公开(公告)日：2019-05-02

申请号：US15856065

申请日：2017-12-28

Applicant: Industrial Technology Research Institute ,  Intellectual Property Innovation Corporation

Inventor： Shu-Wei Kuo ,  Wei-Yuan Cheng ,  Shau-Fei Cheng

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/544 ,  H01L21/67 ,  H01L21/48

CPC classification number: H01L24/75 ,  H01L21/4853 ,  H01L21/67144 ,  H01L23/3185 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/544 ,  H01L24/16 ,  H01L24/81 ,  H01L2223/54426 ,  H01L2224/16165 ,  H01L2224/75753 ,  H01L2224/75756 ,  H01L2224/81121 ,  H01L2224/81136

Abstract: A chip bonding apparatus for bonding a chip and a redistribution structure with each other is provided. The chip bonding apparatus includes a pick and place module and an alignment module. The pick and place module is suitable for picking up and placing the chip. The alignment module is movably connected to the pick and place module. The alignment module includes at least one alignment protrusion, wherein the at least one alignment protrusion extends toward at least one alignment socket included in the redistribution structure. Furthermore, a chip bonding method and a chip package structure are provided.

公开(公告)号：US20190057934A1

公开(公告)日：2019-02-21

申请号：US15853853

申请日：2017-12-25

Applicant: Industrial Technology Research Institute ,  Intellectual Property Innovation Corporation

Inventor： Jie-Mo Lin ,  Shu-Wei Kuo ,  Wei-Yuan Cheng ,  Chen-Tsai Yang

IPC: H01L23/528 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498

Abstract: A redistribution layer structure of the semiconductor package includes a dielectric layer having a thickness, at least one upper conductive wire disposed on a first surface of the dielectric layer, at least one lower conductive wire disposed on a second surface of the dielectric layer, and vias penetrating the dielectric layer and connecting the at least one upper conductive wire and the at least one lower conductive wire. Each via has a cross-section at one upper conductive wire. The cross-section has a third width. The ratio of the third width to the thickness of the dielectric layer is less than or equal to 1. The ratio of the pitch between every two adjacent vias to the third width is greater than or equal to 0.5.

公开(公告)号：US20180122732A1

公开(公告)日：2018-05-03

申请号：US15673422

申请日：2017-08-10

Applicant: Industrial Technology Research Institute

Inventor： Shu-Wei Kuo ,  Chun-Yi Cheng ,  Wei-Yuan Cheng

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00

Abstract: A package structure includes a redistribution layer, a chip, an encapsulant, an under bump supporting layer, an attachment layer and solder balls. The redistribution layer includes a first surface, a second surface opposite to the first surface and a patterned circuit layer disposed on the first surface, wherein an outer surface of the patterned circuit layer and the first surface are coplanar. The chip is disposed on the second surface and electrically connected to the patterned circuit layer. The encapsulant is disposed on the second surface to encapsulate the chip. The under bump supporting layer is disposed on the first surface and includes openings for exposing the outer surface. The attachment layer covers the inner surface of each opening and the exposed portion of the patterned circuit layer. The solder balls are disposed in the openings respectively and electrically connected to the patterned circuit layer.

公开(公告)号：US20180122694A1

公开(公告)日：2018-05-03

申请号：US15597124

申请日：2017-05-16

Applicant: Industrial Technology Research Institute

Inventor： Chun-Yi Cheng ,  Wei-Yuan Cheng ,  Shu-Wei Kuo ,  Yu-Jhen Yang

IPC: H01L21/768 ,  H01L23/31 ,  H01L21/48 ,  H01L23/00 ,  H01L21/02

CPC classification number: H01L23/3107 ,  H01L21/02172 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76832 ,  H01L21/76838 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/81 ,  H01L2221/68359 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/16227 ,  H01L2224/81005 ,  H01L2224/81385 ,  H01L2224/814 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/15311 ,  H01L2924/181

Abstract: A package structure includes a redistribution layer, a chip, an encapsulant, a plurality of under ball release layers, and a plurality of solder balls. The redistribution layer includes a first surface, a second surface opposite to the first surface, and a patterned circuit layer, wherein the patterned circuit layer includes a plurality of pads protruding from the first surface. The chip is disposed on the second surface and electrically connected to the patterned circuit layer. The encapsulant is disposed on the second surface and encapsulates the chip. The under ball release layers cover the pads respectively. The solder balls are disposed on the under ball release layers and electrically connected to the pads.