公开(公告)号：DE102005035166A1

公开(公告)日：2006-05-11

申请号：DE102005035166

申请日：2005-07-27

Applicant: INFINEON TECHNOLOGIES AG ,  ALTIS SEMICONDUCTOR SNC CORBEI

Inventor： BRAUN DANIEL ,  LEUSCHNER RAINER ,  KLOSTERMANN ULRICH

IPC: H01L27/22

公开(公告)号：DE102006008264A1

公开(公告)日：2006-10-05

申请号：DE102006008264

申请日：2006-02-22

Applicant: INFINEON TECHNOLOGIES AG ,  ALTIS SEMICONDUCTOR SNC

Inventor： BRAUN DANIEL ,  MUELLER GERHARD

IPC: G11C11/15

Abstract: The cell has a magnetic channel passage with magnetic regions that are separated by a non-magnetic channel barrier layer. One region has a reference layer with a fixed magnetization, and the other region has a free layer (2) with free magnetizations, which are aligned to a light magnetization axis. The layer (2) is coupled to magnetic fields, and the axis is inclined under an inclination angle relative to conductors. An independent claim is also included for a method of writing in a magneto resistive random access memory (MRAM) cell.

公开(公告)号：GB2422735A

公开(公告)日：2006-08-02

申请号：GB0601186

申请日：2006-01-20

Applicant: INFINEON TECHNOLOGIES AG ,  ALTIS SEMICONDUCTOR SNC

Inventor： KLOSTERMANN ULRICH ,  BRAUN DANIEL

IPC: G11C11/15

Abstract: Magnetoresistive tunnelling junction memory element consists of a first magnetic system R sandwiched between a ferromagnetic tunnelling junction free layer FL1 and at least one other ferromagnetic free layer FL2. The two or more ferromagnetic free layers are antiferromagnetically coupled. The first magnetic system R consists of a ferromagnetic tunnelling junction reference layer having a fixed magnetic moment and is separated from the ferromagnetic tunnelling junction free layer by a tunnelling barrier B1. The tunnelling barrier B1, the tunnelling junction free layer FL1 and the tunnelling junction reference layer form a magnetoresistive tunnelling junction. The first magnetic system R may be formed from a first pinned layer (Ra, fig 3B) antiferromagnetically coupled to a second pinned layer (Rb, fig 3B). Underlayers UL1 and UL2 may be provided to act as diffusion barriers and seed layers for the stack growth. A cap layer CL1 may also be provided. The large distance r between the ferromagnetic free layers FL1 and FL2 means that a conventional spacer layer is rendered superfluous and the memory element can be scaled down without adverse effects on dipole coupling of the free layers.

公开(公告)号：DE102005055436A1

公开(公告)日：2006-06-01

申请号：DE102005055436

申请日：2005-11-21

Applicant: INFINEON TECHNOLOGIES AG ,  ALTIS SEMICONDUCTOR SNC CORBEI

Inventor： BRAUN DANIEL ,  GOGL DIETMAR

IPC: H01L27/22 ,  G11C11/15

Abstract: The chip has a set of magnetoresistive memory cells each including a magnetic tunnel junction having fixed and free magnetic regions. The free magnetic region includes two ferromagnetic layers that are antiferromagnetically coupled, where a coil surrounds the memory chip for creating a magnetic offset field. The regions are stacked in a parallel, overlying relationship separated by a layer of non-magnetic material. An independent claim is also included for a method of writing to a random access memory.

公开(公告)号：DE102005035152A1

公开(公告)日：2006-03-23

申请号：DE102005035152

申请日：2005-07-27

Applicant: INFINEON TECHNOLOGIES AG ,  ALTIS SEMICONDUCTOR SNC CORBEI

Inventor： FERRANT RICHARD ,  BRAUN DANIEL ,  LOUIS PASCAL

IPC: H01L27/22 ,  G11C13/00

Abstract: A MRAM storage device comprises a substrate, on/above of which a plurality of word lines, a plurality of bit lines, a plurality of memory cells, and a plurality of isolation diodes are provided. Each memory cell forms a resistive cross point of one word line and one bit line, respectively. Each memory cell is connected to one isolation diode such that a unidirectional conductive path is formed from a word line to a bit line via the corresponding memory cell, respectively. The substrate, at least a part of the word lines or at least a part of the bit lines, and the isolation diodes are realized as one common monocrystal semiconductor block.

公开(公告)号：DE102005035165A1

公开(公告)日：2006-03-09

申请号：DE102005035165

申请日：2005-07-27

Applicant: INFINEON TECHNOLOGIES AG ,  ALTIS SEMICONDUCTOR SNC CORBEI

Inventor： LEUSCHNER RAINER ,  BRAUN DANIEL ,  LEE GILL YONG ,  KLOSTERMANN ULRICH

IPC: G11C11/16

Abstract: A magnetoresistive or magnetic memory element and a magnetic random access memory having one or more magnetic memory elements. The memory element includes a magnetic tunnel junction including first and a second magnetic layers. The first magnetic layer having a free magnetization. The free magnetization of the first magnetic layer is magnetically coupled to a first current line and a second current line for switching the free magnetization, and a mechanism for applying a static magnetic offset field in the direction of at least one of the first and second current lines.

公开(公告)号：DE102005035164A1

公开(公告)日：2006-03-02

申请号：DE102005035164

申请日：2005-07-27

Applicant: INFINEON TECHNOLOGIES AG ,  ALTIS SEMICONDUCTOR SNC CORBEI

Inventor： BRAUN DANIEL ,  FERRANT RICHARD

IPC: G11C11/16 ,  H01L27/22

Abstract: A magnetic memory element comprising a magnetic storage element having at least one magnetic layer made of a magnetic material and being vertically oriented relative to a wafer surface on which the magnetic memory element is formed, the magnetic layer having a magnetic anisotropy with its magnetization vector being magnetically coupled to at least one current line, and a magnetic sensor element for sensing the magnetization of the at least one magnetic layer of the magnetic storage element comprising at least one magnetic layer having a magnetization vector being magnetically coupled to the magnetization vector of the at least one magnetic layer of the magnetic storage element, the magnetic sensor element being conductively coupled to the at least one current line.