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    METHOD AND DEVICE FOR MODULAR MULTIPLICATION
    11.
    发明申请
    METHOD AND DEVICE FOR MODULAR MULTIPLICATION 审中-公开
    用于模块化乘法的方法和设备

    公开(公告)号：WO03021424A3

    公开(公告)日：2003-09-25

    申请号：PCT/EP0209404

    申请日：2002-08-22

    Applicant: INFINEON TECHNOLOGIES AG ,  ELBE ASTRID ,  JANSSEN NORBERT ,  SEDLAK HOLGER ,  SEIFERT JEAN-PIERRE

    Inventor： ELBE ASTRID ,  JANSSEN NORBERT ,  SEDLAK HOLGER ,  SEIFERT JEAN-PIERRE

    IPC: G06F7/72

    CPC classification number: G06F7/722

    Abstract: The invention relates to a method for modular multiplication of a multiplicand (C) with a multiplicator (M) using a module (N), whereby firstly l multiplication shift values are determined (10), using a multiplication forecast method using l blocks of adjacent multiplicator (M) positions. l Reduction shift values are then determined (13), using a reduction prediction method for the l blocks of multiplicator (M) positions. An intermediate result (Z), from a previous iteration step, the module (N), or a value derived from the module and the multiplicand (C) are processed (16) with the l multiplication shift values and the l reduction shift values to obtain the 2l+1 operands (17). The 2l+1 operands are combined by means of a multi-operand summator (18), to obtain an updated intermediate result (Z') for an iteration step, following the previous iteration step, whereby the iteration is continued until all the multiplicator positions (M) are used. Depending on the number of operands the number of cycles to be calculated may be reduced such that a more rapid calculation of the modular multiplication is possible without an increased hardware complexity.

    Abstract translation: 在使用模数（N）将乘数（C）乘以乘数（M）的方法中，首先，通过考虑乘数（M）的一个位置块的乘法先行方法来计算1个乘数移位值 ），它们相互连接，确定（10）。 然后，通过针对乘数（M）（13）的1个位置块的减少先行方法来获得1个减少移位值。 来自先前迭代步骤的中间结果（Z），模数（N）或从模数导出的值以及被乘数（C）被应用1个乘法移位值和1个减少移位值（16）， 得到2l + 1个操作数（17）。 通过Multioperandenaddierers的装置（18）总结了21 + 1点的操作数以获得更新的中间结果（Z“），用于以下的迭代前面的迭代步骤，迭代继续，直到所执行的乘数的所有数字（M） 是。 根据操作数的数量，要计算的周期数量会减少，因此可以以更大的硬件成本为代价更快地计算模乘。

    DEVICE AND METHOD FOR CONVERTING AND ADDING CIRCUIT
    13.
    发明申请
    DEVICE AND METHOD FOR CONVERTING AND ADDING CIRCUIT 审中-公开
    用于实现和寻址切换的装置和方法

    公开(公告)号：WO2004031938A3

    公开(公告)日：2004-07-01

    申请号：PCT/EP0310596

    申请日：2003-09-23

    Applicant: INFINEON TECHNOLOGIES AG ,  ELBE ASTRID ,  JANSSEN NORBERT ,  SEDLAK HOLGER

    Inventor： ELBE ASTRID ,  JANSSEN NORBERT ,  SEDLAK HOLGER

    IPC: G06F7/38 ,  G06F7/50 ,  G06F7/509 ,  G06F7/72

    CPC classification number: G06F7/509 ,  G06F7/503 ,  G06F7/72 ,  G06F2207/3872 ,  G06F2207/7266 ,  H04L9/003 ,  H04L9/30 ,  H04L2209/12

    Abstract: The invention relates to a device for converting a dual rail input having two effective operand bits and two auxiliary operand bits into a one-hot coded output with three output operands. The device comprises a control device for operating said device in data mode and for operating the device in a preparation mode following said data mode. The device also comprises a logic circuit for combining the two effective operand bits and the two auxiliary operand bits so that two of the three output operands have a value differing from that of the third output operand in the data mode. The device is further configured in such a way as to bring all three output operands to the same value in the preparation mode. The conversion device can be used preferably in a three operand adder as interface between a dual-rail three bit half-adder and a sum-carry stage of a two-bit complete adder in order to achieve the same reliability as in three operand adder fully configured in dual-rail technology despite the fact that the two-bit complete adder is configured in single-rail technology.

    Abstract translation: 用于将包括两个有用操作数位和两个辅助双轨输入到具有三个输出操作数的一热编码输出的装置包括控制装置用于在数据模式下操作的装置和用于在准备模式下操作的装置中， 遵循数据模式。 该装置还包括一个逻辑电路，用于组合所述两个有用的操作数位和两个辅助，使得在数据模式中，三个输出操作数的两个输出操作数具有比第三输出操作数以外的值，并且其中所述装置还被配置为在准备模式中，三个输出操作数 带来相同的价值。 该转换器装置中，优选在三操作数加法器，以便尽管两个位全加器的执行中使用作为双轨三比特半加器和一个二位的全加法器的总和进位级之间的界面 在单轨技术中达到与双轨技术中三操作数加法器的完整版本相同的安全等级。

    REGISTER CELL AND METHOD FOR WRITING INTO SAID REGISTER CELL
    14.
    发明申请
    REGISTER CELL AND METHOD FOR WRITING INTO SAID REGISTER CELL 审中-公开
    寄存器单元和方法写在寄存器单元

    公开(公告)号：WO03081367A3

    公开(公告)日：2004-04-01

    申请号：PCT/EP0302755

    申请日：2003-03-17

    Applicant: INFINEON TECHNOLOGIES AG ,  ELBE ASTRID ,  FISCHER WIELAND ,  JANSSEN NORBERT ,  ROEMER TANJA ,  SEDLAK HOLGER ,  SEIFERT JEAN-PIERRE

    Inventor： ELBE ASTRID ,  FISCHER WIELAND ,  JANSSEN NORBERT ,  ROEMER TANJA ,  SEDLAK HOLGER ,  SEIFERT JEAN-PIERRE

    IPC: G11C7/22 ,  G11C11/41 ,  G11C7/24

    CPC classification number: G11C7/22 ,  G11C2207/007 ,  G11C2207/2227

    Abstract: The invention relates to a register cell which comprises a first input (10) for a data unit to be written into said register cell. The register cell further comprises a second input (12) for a negated data unit to be written into the register cell. A first pair (14) of cross-coupled inverters (14a, 14b) can be coupled with the first input (10) as the first memory circuit. A second pair of cross-coupled inverters (16a, 16b) can be coupled with the second input (12) as the second memory circuit. The use of two cross-coupled pairs of inverters allows to initialize (30) the first input (10) and the second input (12) of the register either at a high voltage status (precharge) or at a low voltage status (discharge) in such a manner as to render the power consumption of the register cell from one cycle to the next more uniform.

    Abstract translation: 甲寄存器单元包括用于第一输入（10），要被写入到所述寄存器单元中的数据单元。 寄存器单元进一步包括用于第二输入（12），要被写入到所述寄存器单元否定数据单元。 到第一输入端（10）是相对地einerstes耦合的反相器对（14）（14A，14B）alserste存储器电路耦合。 带相反耦合的反相器的第二输入端（12）Istein第二对（16A，16B），其耦合到所述第二存储器电路。 使用两个相对连接对反相器的同时允许所述第一输入端（10）作为第二输入和（12）的寄存器或者在高电压状态（预充电）的或低电压状态（放电）来初始化（30），以这样的方式 寄存器单元的所述功率消耗通过一个工作循环到下均质化。

    PROCESSOR AND METHOD FOR SIMULTANEOUSLY DOING A CALCULATION AND CARRYING OUT A COPYING PROCESS
    15.
    发明申请
    PROCESSOR AND METHOD FOR SIMULTANEOUSLY DOING A CALCULATION AND CARRYING OUT A COPYING PROCESS 审中-公开
    处理器和方法同时进行计算及复印件RUN

    公开(公告)号：WO03104975A2

    公开(公告)日：2003-12-18

    申请号：PCT/EP0305642

    申请日：2003-05-28

    Applicant: INFINEON TECHNOLOGIES AG ,  ELBE ASTRID ,  FISCHER WIELAND ,  JANSSEN NORBERT ,  SEDLAK HOLGER ,  SEIFERT JEAN-PIERRE

    Inventor： ELBE ASTRID ,  FISCHER WIELAND ,  JANSSEN NORBERT ,  SEDLAK HOLGER ,  SEIFERT JEAN-PIERRE

    IPC: G06F9/302 ,  G06F9/308

    CPC classification number: G06F9/3001 ,  G06F9/30018

    Abstract: Disclosed is a processor comprising a source register (10) with a content, a destination register (12), an arithmetic unit (14) doing a calculation by using the content of the source register, said calculation being done in several cycles and only a portion of the content of the source register being usable in each cycle, a data bus (18) which is connected to the source register (10), the destination register (12), and the arithmetic unit (14), and a processor control unit which is operable so as to feed the content of the source register in portions to the arithmetic unit and the destination register via the data bus during the calculation process such that the content of the source register is written in the destination register once the calculation is done. The inventive processor makes it possible to copy a register for long operands that are to be processed portion by portion from a source register to a destination register via a limited data bus without using any additional machine cycles.

    Abstract translation: 一种处理器，包括具有源寄存器内容的源寄存器（10），用于使用所述源寄存器的内容执行计算，其中，所述计算可以以若干个计算周期中的每个周期仅一部分来执行，并且其特征在于，目的地寄存器（12），运算单元（14） 使用源寄存器的内容，其被连接到源寄存器（10）的数据总线（18），目的地寄存器（12）和所述算术单元（14），以及处理器控制。 处理器的控制是用于通过数据总线部分的源寄存器的内容到计算单元上，一方面与目标寄存器在另一方面的计算过程中提供，从而根据所述源寄存器的内容到目的寄存器的计算的实施方式写入。 这使得有可能实现从源寄存器的寄存器复制到目的地寄存器，用于在有限的总线而无需额外的机器周期为要被处理的操作数长的部分。

    MICROPROCESSOR CIRCUIT FOR DATA CARRIERS AND A METHOD FOR ORGANISING ACCESS TO DATA STORED IN A MEMORY
    16.
    发明申请
    MICROPROCESSOR CIRCUIT FOR DATA CARRIERS AND A METHOD FOR ORGANISING ACCESS TO DATA STORED IN A MEMORY 审中-公开
    微处理器电路介质和方法组织访问存储在存储器中的数据

    公开(公告)号：WO02063463A3

    公开(公告)日：2003-02-06

    申请号：PCT/DE0200256

    申请日：2002-01-25

    Applicant: INFINEON TECHNOLOGIES AG ,  BRUECKLMAYR FRANZ-JOSEF ,  FRIEDINGER HANS ,  SEDLAK HOLGER ,  MAY CHRISTIAN

    Inventor： BRUECKLMAYR FRANZ-JOSEF ,  FRIEDINGER HANS ,  SEDLAK HOLGER ,  MAY CHRISTIAN

    IPC: G06F12/14 ,  G06F21/24

    CPC classification number: G06F12/1483 ,  G06F12/1441

    Abstract: The invention relates to a microprocessor circuit for organising access to data or programmes that have been stored in a memory. Said circuit comprises at least one microprocessor, a memory for an operating system and at least one memory for free programming using individual external programmes. The memory used for free programming has several memory areas containing corresponding address spaces, a qualifier being assigned to each address space. The microprocessor circuit also has means, which prior to the respective addressing of a memory area, load each qualifier assigned to a respective memory area into a first auxiliary register and load the qualifier of the addressed memory area into a second auxiliary register and which then compare the first and second auxiliary registers. At least one bit sequence containing access authorisations is also assigned to each address space of a memory area, which allows code commands and sensitive data to be protected from write access emanating from external programmes.

    Abstract translation: 本发明提出一种具有至少一个微处理器，用于操作系统的存储器和之前使用单独的外部程序对自由编程的至少一个存储器，其中所述存储器中用于自由编程多个与各存储区组织到存储器存储的数据或程序的访问的微处理器电路 提供的地址空间，其中每一个地址空间被分配的标识符。 微处理器电路还包括用于加载存储器区域的寻址之前在每种情况下分别分配的存储区域的标志为第一辅助寄存器和被寻址的存储器区域的识别符加载到第二辅助寄存器，并且使第一和第二辅助寄存器的比较装置。 它进一步提供分配含有的存储区域，其中代码的命令和敏感的数据从写访问可被保护免受其他外部程序的每个地址空间中的至少一个的访问权限比特序列。

    MODULAR MULTIPLICATION WITH PARALLEL CALCULATION OF LOOK-AHEAD PARAMETERS
    19.
    发明申请
    MODULAR MULTIPLICATION WITH PARALLEL CALCULATION OF LOOK-AHEAD PARAMETERS 审中-公开
    与估计的参数并行计算模乘

    公开(公告)号：WO2004059515A3

    公开(公告)日：2005-02-10

    申请号：PCT/EP0314135

    申请日：2003-12-12

    Applicant: INFINEON TECHNOLOGIES AG ,  FISCHER WIELAND ,  SEDLAK HOLGER ,  SEIFERT JEAN-PIERRE

    Inventor： FISCHER WIELAND ,  SEDLAK HOLGER ,  SEIFERT JEAN-PIERRE

    IPC: G06F7/72

    CPC classification number: G06F7/722

    Abstract: The device for calculation of a multiplication of a multiplier and a multiplicand consists of a device (40) for performing an exact three operand addition in addition to a device(412) for performing an approximated operand addition, and a device (417) for calculating look-ahead parameters using an approximated intermediate result (414) calculated by the device (412). The device for performing the exact three operand addition is also configured in such a way that it can carry out an exact three-operand addition (400') in a current iteration step using the exact intermediate result for the current iteration step and using the look-ahead parameters, calculated by the device (417), for the current iteration step. As a result, the long-number calculator can continuously perform three operand additions and is no longer required to lie idle while look-ahead parameters are calculated. This results in a significant increase in performance when cryptographic calculations are performed.

    Abstract translation: 用于计算乘数的乘法和被乘数的装置包括用于计算当前先行用于执行用于执行的近似操作数加法确切3次操作数加法和装置（412）的装置（400），以及装置（417） 参数，使用的装置（412）计算出的近似中间结果（414）。 用于执行精确3个操作数加法的装置被使用的确切中间结果为当前迭代步骤和使用该装置的（417）还形成为在当前迭代步骤的精确3次操作数加法（400“） 当前迭代计算提前参数来执行。 因此，长数计算单元可以执行三个连续操作数加法和不再具有同时计算提前参数静置。 这导致性能加密计算一个显著上升。

    HALF-ADDER
    20.
    发明申请
    HALF-ADDER 审中-公开
    半加器

    公开(公告)号：WO2004077196A2

    公开(公告)日：2004-09-10

    申请号：PCT/EP2004001874

    申请日：2004-02-25

    Applicant: INFINEON TECHNOLOGIES AG ,  ELBE ASTRID ,  JANSSEN NORBERT ,  SEDLAK HOLGER

    Inventor： ELBE ASTRID ,  JANSSEN NORBERT ,  SEDLAK HOLGER

    IPC: G06F20060101 ,  G06F7/50 ,  G06F7/501 ,  G06F7/60 ,  G09C1/00 ,  G06F

    CPC classification number: G06F7/607 ,  G06F7/501 ,  G06F2207/3872 ,  G06F2207/7266

    Abstract: The invention relates to a half-adder for adding bits of at least two input operands in order to obtain at least two output bits. The inventive half-adder comprised an input stage (10), a plurality of commutation stages (12a, 12b, 12c) and an output stage (14a, 14b, 14c) arranged after each commutation stage, respectively. In a data mode, the commutation stages can operate either for delivering a bit or an inverse bit of an output (18a, 18b, 18c) on the output stage arranged after the corresponding commutation stage. The output stage modifies an output bit with respect to the past preparation mode on the basis of the bit contained in the corresponding commutation stage and completes a complementary bit from the past preparation mode. The half-adder circuit has a surface effectiveness using complete dual-rail logic and being protected against any cryptographic attack.

    Abstract translation: 用于添加位的至少两个输入操作数的，以获得至少两个输出位，除了一个输入级（10）的本发明的半加器包括多个交换级（12A，12B，12C）和每个声级的设置的输出级的下游（图14A，14B，14C） ， 在数据模式中，开关电路用于传送任一个比特或比特反转在输出（18A，18B，18C）连接到输出级，其被布置在下游的相应档位的。 然后，输出级从各开关级接收基于所述比特的变化，输出比特相比之前的准备模式，并从前面的准备模式增加了互补位。 半加器电路是区域有效，因为它并不需要完整的双轨逻辑，但反对密码攻击的安全。

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