公开(公告)号：JP2004088098A

公开(公告)日：2004-03-18

申请号：JP2003287154

申请日：2003-08-05

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHUDZIK MICHAEL P ,  BEINTNER JOCHEN ,  RAMACHANDORA DEIVAKARUNI ,  JAMMY RAJARAO

IPC: H01L21/334 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10867 ,  H01L27/10841 ,  H01L29/66181

Abstract: PROBLEM TO BE SOLVED: To provide a method to form a three-dimensional electrical structure which brings two circuit elements separated in the horizontal and vertical directions into contact, regarding the formation of structures including a DRAM cell comprising a vertical transistor.
SOLUTION: A temporary insulator layer is deposited, and a vertical spacer is formed on the trench walls above the temporary insulator, then the insulator is removed to expose the substrate walls. Next, dopant is diffused into the substrate walls to form a self-aligned extension of a buried strap, and a final gate insulator is deposited, then the upper portion of a DRAM cell is formed.
COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2007133395A

公开(公告)日：2007-05-31

申请号：JP2006294951

申请日：2006-10-30

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： LIEBMANN LARS W ,  BEINTNER JOCHEN

IPC: G03F1/08 ,  H01L21/027 ,  H01L21/82

CPC classification number: G03F1/70

Abstract: PROBLEM TO BE SOLVED: To provide a mask design for a sidewall image transfer process that compensates disadvantages upon forming an integrated circuit by a photolithography mask. SOLUTION: An edge based image transfer process includes depositing an etch-masking medium, for example, a nitride on the sidewall of a mesa and removing the mesa so as to leave the sidewall structure. A method is provided for converting an integrated circuit design into a set of masks for fabrication of an integrated circuit that optimizes use of the edge base imaged transfer mask process. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供用于通过光刻掩模形成集成电路来补偿缺点的侧壁图像转印工艺的掩模设计。 解决方案：基于边缘的图像转移过程包括在台面的侧壁上沉积蚀刻掩蔽介质，例如氮化物，并去除台面，以便离开侧壁结构。 提供了一种用于将集成电路设计转换成用于制造集成电路的一组掩模的方法，该集成电路优化了边缘基底成像传送掩模处理的使用。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JPH11176930A

公开(公告)日：1999-07-02

申请号：JP26992298

申请日：1998-09-24

Applicant: SIEMENS AG ,  IBM

Inventor： GRUENING ULRIKE ,  BEINTNER JOCHEN ,  RADENS CARL

IPC: H01L21/76 ,  H01L21/308 ,  H01L21/31 ,  H01L21/316 ,  H01L21/318 ,  H01L21/763 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a layer which is uniform in flatness and thickness on a semiconductor chip or on a semiconductor device provided with a trench. SOLUTION: An oxide thermal pad layer 104 is formed on a semiconductor substrate 102 through a thermal oxidation method, a nitride insulating layer 106, a buffer layer 108 of oxide or preferably TEOS(tetraethyl oxosilane), and a SiN mask layer 110 are formed thereon through a CVD(chemical vapor deposition) method, and a hard mask layer 112 containing BSG(borosilicate glass) or TEOS is formed on the mask layer 110. Then, a semiconductor device is manufactured, a trench is provided to the device, filler is filled, a polishing is carried out up to a pad stop, and an etching operation is carried out using the buffer layer as an etching stopper for removing the pad stop and the buffer layer, whereby a surface layer which is nearly flat and uniform in thickness can be obtained.

公开(公告)号：JP2000040797A

公开(公告)日：2000-02-08

申请号：JP17017799

申请日：1999-06-16

Applicant: SIEMENS AG ,  IBM ,  TOSHIBA CORP

Inventor： RENGARAJAN RAJESH ,  INOUE HIROFUMI ,  SRINIVASAN RADHIKA ,  BEINTNER JOCHEN

IPC: H01L21/76 ,  H01L21/762 ,  H01L27/08

Abstract: PROBLEM TO BE SOLVED: To provide a method of forming semiconductor elements, which are electrically insulated from each other within a silicon base body, and a semiconductor structure manufactured by this method. SOLUTION: This method of forming semiconductor elements is executed by having trenches formed in the selected regions of a silicon base body 10 and depositing a barrier material on the sidewalls of the trenches. The barrier material is removed from the first sidewall parts 34 of the trenches, while the barrier material is left on the second sidewall parts 32 of the trenches and a barrier layer 26 is formed in each trench. A dielectric material 38 is deposited in the trenches and the dielectric material is deposited on each of the exposed first sidewall parts within the trenches and the barrier layers within the trenches. The dielectric material is annealed in an oxidizing atmosphere and is highly compacted, and the second sidewall parts of the trenches are prevented from being oxidized by the barrier layers. A plurality of the semiconductor elements are formed within the silicon base body, and the elements are electrically insulated from each other by the dielectric material.

公开(公告)号：JPH11330402A

公开(公告)日：1999-11-30

申请号：JP9246899

申请日：1999-03-31

Applicant: SIEMENS AG ,  IBM

Inventor： GRUENING ULRIKE ,  JAIPRAKASH VENKATACHALAM C ,  BRONNER GARY ,  RADENS CARL ,  BEINTNER JOCHEN

IPC: H01L27/108 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To reduce the diffusion of the height of an embedded strap by making the depression extending below the surface of the substrate in a filling material, to determine the top surface of a buried strap and by making a recess extending below the top surface of the embedded strap in a collar to determine the bottom side surface. SOLUTION: A substrate includes a partially completed trench capacitor. A collar 110 is made on the upper portion of the trench capacitor. A trench 108 is filled with a filling material 112 and the inner sidewall of the collar is lined with the filling material 112. A recess having a predetermined depth is made in the filling material 112. The depth of the recess actually determines the top portion of an embedded strap. A hole is made in the collar to the depth of 120 below the top surface 118 of the filling material 112. A layer 122 is removed from the side of the trench 108 and the top surface of a semiconductor device 100, while a recessed region 124 filled with the material of the layer 122 is left.

公开(公告)号：JP2005197749A

公开(公告)日：2005-07-21

申请号：JP2005002025

申请日：2005-01-07

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BEINTNER JOCHEN ,  DIVAKARUNI RAMA ,  JAMMY RAJARAO

IPC: H01L21/8242 ,  H01L21/762 ,  H01L27/108 ,  H01L29/76

CPC classification number: H01L27/10864 ,  H01L27/10841 ,  H01L27/10894

Abstract: PROBLEM TO BE SOLVED: To provide a structure for a perpendicular-type DRAM capable of being integrated into a process flow, using a flat surface device.
SOLUTION: A method of manufacturing an integrated circuit device comprises steps of etching a trench in a substrate; and forming DRAM cells which include a build-up capacitor 24 at a lower edge and a perpendicular-type MOSFET having a gate conductor 30 covering the build-up capacitor 24 and a boron doped channel. The method further comprises a step of forming a trench adjacent to the DRAM cells and a silicon acid nitriding isolation liner at either side of the DRAM cells. Next, an isolation region is formed in the trench at either side of the DRAM cells. Thereafter, the DRAM cells, including a boron-containing channel region are exposed to a high temperature caused by heat treatment to form a supporting device and so on. A nitride containing isolation liner reduces the isolation of boron in a channel region as compared with an oxide-containing isolation liner essentially without nitrogen.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种能够使用平面装置集成到工艺流程中的垂直型DRAM的结构。 解决方案：一种制造集成电路器件的方法包括以下步骤：蚀刻衬底中的沟槽; 并且在下边缘处形成包括积聚电容器24的DRAM单元和具有覆盖积层电容器24的栅极导体30和掺杂硼的沟道的垂直型MOSFET。 该方法还包括在DRAM单元的任一侧形成与DRAM单元相邻的沟槽和硅酸氮化隔离衬垫的步骤。 接下来，在DRAM单元的任一侧的沟槽中形成隔离区。 此后，包括含硼沟道区的DRAM单元暴露于由热处理引起的高温以形成支撑装置等。 与基本上不含氮的含氧化物的隔离衬垫相比，含氮化物的隔离衬垫减少了沟道区域中硼的分离。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2004336049A

公开(公告)日：2004-11-25

申请号：JP2004135830

申请日：2004-04-30

Applicant: Infineon Technol North America Corp ,  Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation ,  インフィニオン テクノロジーズ ノース アメリカ コーポレイション Infineon Technologies North America Corp.

Inventor： BEINTNER JOCHEN ,  LI YUJUN ,  MOUMEN NAIM ,  WRSCHKA PORSHIA SHANE

IPC: H01L29/423 ,  H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/6659 ,  H01L21/26586 ,  H01L21/28044 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/49 ,  H01L29/665 ,  Y10S438/933

Abstract: PROBLEM TO BE SOLVED: To provide a structure and manufacturing method of a notch gate field effect transistor which can cope with a problem of device (element) reliability.
SOLUTION: A gate dielectric 14 (for example, gate oxide film) is preferably formed on a surface of an active field 10 on a semiconductor substrate defined by a separation trench area 12. Next, a polysilicon layer 16 is accumulated on the gate dielectric. After the above process, a silicon germanium (SiGe) layer 18 is accumulated. Next, a side wall of the polysilicon layer is selectively etched in the transverse direction against the SiGe layer, and a notch gate conductor structure having the SiGe layer wider than the polysilicon layer thereunder is formed. A side wall spacer 26 is formed preferably on the side wall of the SiGe layer and the polysilicon layer. In order to reduce the resistance of a gate conductor 24, preferably, a silicide layer 28 is formed as self-alignment silicide from the polysilicon layer accumulated on the SiGe layer.
COPYRIGHT: (C)2005,JPO&NCIPI

公开(公告)号：WO2007035788A3

公开(公告)日：2008-11-20

申请号：PCT/US2006036575

申请日：2006-09-19

Applicant: IBM ,  BEINTNER JOCHEN ,  LUDWIG THOMAS ,  NOWAK EDWARD J

Inventor： BEINTNER JOCHEN ,  LUDWIG THOMAS ,  NOWAK EDWARD J

IPC: H01L21/00

CPC classification number: H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785

Abstract: A method, structure and alignment procedure, for forming a finFET. The method including, defining a first fin of the finFET with a first mask and defining a second fin of the finFET with a second mask. The structure including integral first and second fins of single-crystal semiconductor material and longitudinal axes of the first and second fins aligned in the same crystal direction but offset from each other. The alignment procedure including simultaneously aligning alignment marks on a gate mask to alignment targets formed separately by a first masked used to define the first fin and a second mask used to define the second fin.

Abstract translation: 用于形成finFET的方法，结构和取向程序。 该方法包括：用第一掩模限定finFET的第一鳍片，并用第二掩模限定finFET的第二鳍片。 该结构包括单晶半导体材料的整体第一和第二鳍片以及第一和第二鳍片的纵向轴线在相同的晶体方向上排列但彼此偏移。 对准过程包括同时将栅极掩模上的对准标记对准由通过用于限定第一鳍片的第一掩模单独形成的对准靶和用于限定第二鳍片的第二掩模。

公开(公告)号：WO2005079182A3

公开(公告)日：2006-04-06

申请号：PCT/US2004001721

申请日：2004-01-22

Applicant: IBM ,  BEINTNER JOCHEN ,  CHIDAMBARRAO DURESETI ,  DIVKARUNI RAMACHANDRA

Inventor： BEINTNER JOCHEN ,  CHIDAMBARRAO DURESETI ,  DIVKARUNI RAMACHANDRA

IPC: H01L29/786 ,  H01L21/336 ,  H01L21/8238

CPC classification number: H01L29/78642 ,  H01L21/2257 ,  H01L29/66787

Abstract: A new class of high-density, vertical Fin-FET devices that exhibit low contact resistance is described. These vertical Fin-FET devices have vertical silicon "fins" (12A) that act as the transistor body. Doped source and drain regions (26A, 28A) are formed at the bottoms and tops, respectively, of the fins (12A). Gates (24A, 24B) are formed along sidewalls of the fins. Current flows vertically through the fins (12A) between the source and drain regions (26A, 28A) when an appropriate bias is applied to the gates (24A, 24B). An integrated process for forming pFET, nFET, multi-fin, single-fin, multi-gate and double-gate vertical Fin-FETs simultaneously is described.

Abstract translation: 描述了一种新型的具有低接触电阻的高密度垂直Fin-FET器件。 这些垂直Fin-FET器件具有用作晶体管体的垂直硅“鳍”（12A）。 掺杂的源极和漏极区域（26A，28A）分别形成在鳍片（12A）的底部和顶部。 盖板（24A，24B）沿翅片的侧壁形成。 当适当的偏压被施加到栅极（24A，24B）时，电流垂直地流过源极和漏极区域（26A，28A）之间的鳍片（12A）。 描述了同时形成pFET，nFET，多鳍，单鳍，多栅极和双栅极垂直鳍FET的集成工艺。

公开(公告)号：DE10334946A1

公开(公告)日：2004-03-18

申请号：DE10334946

申请日：2003-07-31

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： BEINTNER JOCHEN ,  CHUDZIK MICHAEL PATRICK ,  RAJARAO JAMMY ,  DIVAKARUNI RAMACHANDRA

IPC: H01L21/334 ,  H01L21/8242 ,  H01L27/108

Abstract: In a vertical-transistor DRAM cell, the problem of making a reliable electrical connection between the node of the deep trench capacitor and the lower electrode of the vertical transistor is solved by; depositing a temporary insulator layer, forming a vertical spacer on the trench walls above the temporary insulator, then stripping the insulator to expose the substrate walls; diffusing dopant into the substrate walls to form a self-aligned extension of the buried strap; depositing the final gate insulator; and then forming the upper portion of the DRAM cell.