公开(公告)号：DE60104015D1

公开(公告)日：2004-07-29

申请号：DE60104015

申请日：2001-08-30

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： LEHMANN GUNTHER ,  FRANKOWSKY GERD ,  HSU LOUIS L ,  REITH ARMIN

IPC: G01R31/3183 ,  G01R31/319 ,  G11C29/10 ,  G11C29/56 ,  G11C29/00

Abstract: An automatic method for the generation of a logical hardware test pattern in memory circuits is based on a given physical pattern. The method includes backwards transformation from a given set of logical data patterns. Since the method is automatic, no knowledge of data scrambling inside the memory circuit is required.

公开(公告)号：DE10261327A1

公开(公告)日：2003-08-07

申请号：DE10261327

申请日：2002-12-27

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： FRANKOWSKY GERD ,  HOKENMAIER WOLFGANG ,  HANSON DAVID R ,  LEHMANN GUNTHER

IPC: G11C7/18 ,  G11C11/4097 ,  G11C29/00

Abstract: A memory is provided having an array of rows and columns of memory cells. The memory includes plurality of sense amplifiers, each one having a true terminal and a compliment terminal. The memory also includes a plurality of pairs of twisted bit lines, each one of the pairs of lines being coupled to true and compliment terminals of a corresponding one of the plurality of sense amplifiers. A plurality of word lines is provided, each one being connected to a corresponding one of the rows of memory cells. An address logic section is fed by column address signals, fed to the bit lines, and row address signals, fed to the word lines, for producing invert/non-invert signals in accordance with the fed row and column address signals. The memory includes a plurality of inverters each one being coupled to a corresponding one of the sense amplifiers for inverting data fed to or read from the sense amplifier selectively in accordance with the invert/non-invert signals produced by the address logic.