公开(公告)号：US20150187942A1

公开(公告)日：2015-07-02

申请号：US14407263

申请日：2012-07-06

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huilong Zhu ,  Zhijiong Luo ,  Haizhou Yin ,  Qingqing Liang

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/161 ,  H01L29/04 ,  H01L21/324 ,  H01L21/762 ,  H01L21/02 ,  H01L21/265 ,  H01L21/306 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/7849 ,  H01L21/0245 ,  H01L21/02513 ,  H01L21/265 ,  H01L21/30604 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/76254 ,  H01L21/76283 ,  H01L29/04 ,  H01L29/0653 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/66568 ,  H01L29/66772 ,  H01L29/732 ,  H01L29/7371 ,  H01L29/78654

Abstract: The present invention discloses a semiconductor structure and a method for manufacturing the same, which comprises providing a substrate, and forming a stress layer, a buried oxide layer, and an SOI layer on the substrate; forming a doped region of the stress layer arranged in a specific position in the stress layer; forming an oxide layer and a nitride layer on the SOI layer, and forming a first trench that etches the nitride layer, the oxide layer, the SOI layer, and the buried oxide layer, and stops on the upper surface of the stress layer, and exposes at least part of the doped region of the stress layer; forming a cavity by wet etching through the first trench to remove the doped region of the stress layer; forming a polycrystalline silicon region of the stress layer and a second trench by filling the cavity with polycrystalline silicon and etching back; forming an isolation region by filling the second trench. The semiconductor structure and the method for manufacturing the same disclosed in the present invention provide a favorable stress for the channel of the semiconductor device by introducing a stress layer and a stress induced zone set at specific positions depending on device type to help improving the performance of the semiconductor device.

Abstract translation: 本发明公开了一种半导体结构及其制造方法，其特征在于，在基板上设置基板，形成应力层，埋入氧化物层，SOI层， 在应力层中形成布置在特定位置的应力层的掺杂区域; 在所述SOI层上形成氧化物层和氮化物层，形成蚀刻所述氮化物层，所述氧化物层，所述SOI层和所述埋入氧化物层的第一沟槽，并停止在所述应力层的上表面上，以及 暴露应力层的掺杂区域的至少一部分; 通过所述第一沟槽的湿蚀刻形成空腔以移除所述应力层的掺杂区域; 通过用多晶硅填充空腔并回蚀而形成应力层的多晶硅区域和第二沟槽; 通过填充第二沟槽形成隔离区域。 在本发明中公开的半导体结构及其制造方法通过根据器件类型在特定位置引入应力层和应力诱导区域来为半导体器件的沟道提供有利的应力，以有助于提高 半导体器件。

公开(公告)号：US08829576B2

公开(公告)日：2014-09-09

申请号：US14001216

申请日：2012-11-27

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huilong Zhu ,  Haizhou Yin ,  Zhijiong Luo

IPC: H01L29/76 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/7848 ,  H01L21/764 ,  H01L21/823412 ,  H01L21/823468 ,  H01L21/823481 ,  H01L21/84 ,  H01L29/66636 ,  H01L29/78654

Abstract: The present invention provides a semiconductor structure comprising a substrate, a gate stack, a sidewall, a base region, source/drain regions, and a support structure, wherein: the base region is located above the substrate, and is separated from the substrate by the void; said support structure is located on both sides of the void, in which part of the support isolation structure is connected with the substrate; the gate stack is located above the base region, said sidewall surrounding the gate stack; said source/drain regions are located on both sides of the gate stack, the base region and the support isolation structure, in which the stress in the source/drain regions first gradually increases and then gradually decreases along the height direction from the bottom. The present invention also provides a manufacturing method for the semiconductor structure. The present invention is beneficial to suppress the short channel effect, as well as to provide an optimum stress to the channel.

Abstract translation: 本发明提供了一种半导体结构，其包括基板，栅极叠层，侧壁，基极区域，源极/漏极区域和支撑结构，其中：基极区域位于衬底上方，并且通过 虚空; 所述支撑结构位于所述空隙的两侧，所述支撑隔离结构的一部分与所述基板连接; 所述栅极堆叠位于所述基极区域的上方，所述侧壁围绕所述栅极叠层; 所述源极/漏极区域位于栅极叠层，基极区域和支撑隔离结构的两侧，其中源极/漏极区域中的应力首先逐渐增加，然后沿着从底部的高度方向逐渐减小。 本发明还提供了一种半导体结构的制造方法。 本发明有利于抑制短通道效应，以及为通道提供最佳应力。

公开(公告)号：US09853153B2

公开(公告)日：2017-12-26

申请号：US14437401

申请日：2012-11-27

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huilong Zhu ,  Zhijiong Luo ,  Haizhou Yin ,  Qingqing Liang

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L21/321 ,  H01L21/84 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L21/308

CPC classification number: H01L29/7848 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/3083 ,  H01L21/311 ,  H01L21/32115 ,  H01L21/845 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/785

Abstract: The present invention provides a method of manufacturing a fin field effect transistor, comprising: providing an SOI substrate comprising a substrate layer (100), a BOX layer (120) and an SOI layer (130); forming a basic fin structure from an SOI layer; forming source/drain regions (110) on both sides of the basic fin structure; forming a fin structure between the source/drain regions (110) from a basic fin structure; and forming a gate stack across the fin structure. The method of manufacturing a fin field effect transistor provided in the present invention can integrate a high-k gate dielectric layer, a metal gate, and stressed source/drain regions into the fin field effect transistor to enhance the performance of the semiconductor device.