公开(公告)号：EP3462491A1

公开(公告)日：2019-04-03

申请号：EP18191579.4

申请日：2018-08-29

Applicant: INTEL Corporation

Inventor： JHA, Chandra M. ,  LI, Eric J. ,  LI, Zhaozhi ,  NICKERSON, Robert M.

IPC: H01L25/10 ,  H01L23/31 ,  H01L23/373

Abstract: A device package and a method of forming the device package are described. The device package has a package layer disposed on a substrate. The package layer includes a mold layer surrounding solder balls and a die. The device package also has a trench disposed in the mold layer to surround the die of the package layer. The device package further includes a conductive layer disposed on a top surface of the die. The conductive layer is disposed over the top surface of the die and in the trench of the package layer. The trench may have a specified distance between the die edges, and a specified width and a specified depth based on the conductive layer. The device package may include an interposer with solder balls disposed on the conductive layer and above the package layer, and an underfill layer disposed between the interposer and the package layer.