公开(公告)号：US20180293490A1

公开(公告)日：2018-10-11

申请号：US15482793

申请日：2017-04-09

Applicant: Intel Corporation

Inventor： Liwei Ma ,  Nadathur Rajagopalan Satish ,  Jeremy Bottleson ,  Farshad Akhbari ,  Eriko Nurvitadhi ,  Chandrasekaran Sakthivel ,  Barath Lakshmanan ,  Jingyi Jin ,  Justin E. Gottschlich ,  Michael Strickland

IPC: G06N3/08 ,  G06F9/50

CPC classification number: G06N3/0445 ,  G06F9/5038 ,  G06F2209/5021 ,  G06N3/0454 ,  G06N3/063 ,  G06N3/084

Abstract: An apparatus to facilitate workload scheduling is disclosed. The apparatus includes one or more clients, one or more processing units to processes workloads received from the one or more clients, including hardware resources and scheduling logic to schedule direct access of the hardware resources to the one or more clients to process the workloads.

公开(公告)号：US11948224B2

公开(公告)日：2024-04-02

申请号：US17978573

申请日：2022-11-01

Applicant: Intel Corporation

Inventor： Elmoustapha Ould-Ahmed-Vall ,  Sara S. Baghsorkhi ,  Anbang Yao ,  Kevin Nealis ,  Xiaoming Chen ,  Altug Koker ,  Abhishek R. Appu ,  John C. Weast ,  Mike B. Macpherson ,  Dukhwan Kim ,  Linda L. Hurd ,  Ben J. Ashbaugh ,  Barath Lakshmanan ,  Liwei Ma ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland

IPC: G06T1/20 ,  G06F3/14 ,  G06F7/483 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06N3/044 ,  G06N3/045 ,  G06N3/063 ,  G06N3/08 ,  G06N3/084 ,  G06N20/00 ,  G06T1/60 ,  G06T15/00

CPC classification number: G06T1/20 ,  G06F7/483 ,  G06F9/30014 ,  G06F9/30185 ,  G06F9/3863 ,  G06F9/5044 ,  G06N3/044 ,  G06N3/045 ,  G06N3/063 ,  G06N3/084 ,  G06N20/00 ,  G06F3/14 ,  G06T1/60 ,  G06T15/005

Abstract: One embodiment provides an apparatus comprising a memory stack including multiple memory dies and a parallel processor including a plurality of multiprocessors. Each multiprocessor has a single instruction, multiple thread (SIMT) architecture, the parallel processor coupled to the memory stack via one or more memory interfaces. At least one multiprocessor comprises a multiply-accumulate circuit to perform multiply-accumulate operations on matrix data in a stage of a neural network implementation to produce a result matrix comprising a plurality of matrix data elements at a first precision, precision tracking logic to evaluate metrics associated with the matrix data elements and indicate if an optimization is to be performed for representing data at a second stage of the neural network implementation, and a numerical transform unit to dynamically perform a numerical transform operation on the matrix data elements based on the indication to produce transformed matrix data elements at a second precision.

公开(公告)号：US20240062414A1

公开(公告)日：2024-02-22

申请号：US18465683

申请日：2023-09-12

Applicant: Intel Corporation

Inventor： Liwei Ma

IPC: G06T7/73 ,  G06N3/08

CPC classification number: G06T7/73 ,  G06N3/08 ,  G06T2207/20081 ,  G06T2207/20084 ,  G06T2207/30244

Abstract: A mechanism is described for facilitating training and deploying of pose regression in neural networks in autonomous machines. A method, as described herein, includes facilitating capturing, by an image capturing device of a computing device, one or more images of one or more objects, where the one or more images include one or more training images associated with a neural network. The method may further include continuously estimating, in real-time, a present orientation of the computing device, where estimating includes continuously detecting a real-time view field as viewed by the image capturing device and based on the one or more images. The method may further include applying pose regression relating to the image capturing device using the real-time view field.

公开(公告)号：US20240013337A1

公开(公告)日：2024-01-11

申请号：US18351898

申请日：2023-07-13

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  John C. Weast ,  Mike B. Macpherson ,  Linda L. Hurd ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Prasoonkumar Surti ,  Chandrasekaran Sakthivel ,  Liwei Ma ,  Elmoustapha Ould-Ahmed-Vall ,  Kamal Sinha ,  Joydeep Ray ,  Balaji Vembu ,  Sanjeev Jahagirdar ,  Vasanth Ranganathan ,  Dukhwan Kim

IPC: G06T1/20 ,  G06F9/46 ,  G06N3/063 ,  G06N3/045 ,  G06N3/08

CPC classification number: G06T1/20 ,  G06F9/46 ,  G06N3/063 ,  G06N3/045 ,  G06N3/08 ,  G06N3/084

Abstract: A mechanism is described for detecting, at training time, information related to one or more tasks to be performed by the one or more processors according to a training dataset for a neural network, analyzing the information to determine one or more portions of hardware of a processor of the one or more processors that is configurable to support the one or more tasks, configuring the hardware to pre-select the one or more portions to perform the one or more tasks, while other portions of the hardware remain available for other tasks, and monitoring utilization of the hardware via a hardware unit of the graphics processor and, via a scheduler of the graphics processor, adjusting allocation of the one or more tasks to the one or more portions of the hardware based on the utilization.

公开(公告)号：US20230315481A1

公开(公告)日：2023-10-05

申请号：US18312079

申请日：2023-05-04

Applicant: Intel Corporation

Inventor： ELMOUSTAPHA OULD-AHMED-VALL ,  BARATH LAKSHMANAN ,  TATIANA SHPEISMAN ,  Joydeep Ray ,  Ping T. Tang ,  Michael Strickland ,  Xiaoming Chen ,  Anbang Yao ,  Ben J. Ashbaugh ,  Linda L. Hurd ,  Liwei Ma

IPC: G06F9/38 ,  G06F9/30 ,  G06F13/42 ,  G06F13/40 ,  G06N20/00 ,  G06T1/20 ,  G06N3/063 ,  G06N3/084 ,  G06N20/10 ,  G06N3/044 ,  G06N3/045 ,  G06F9/50 ,  G06F15/80 ,  G06N3/00

CPC classification number: G06F9/3887 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30094 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3016 ,  G06F9/3851 ,  G06F9/3891 ,  G06F9/50 ,  G06F13/4068 ,  G06F13/4282 ,  G06F15/80 ,  G06N3/00 ,  G06N3/044 ,  G06N3/045 ,  G06N3/063 ,  G06N3/084 ,  G06N20/00 ,  G06N20/10 ,  G06T1/20 ,  G06F2213/0026

Abstract: Described herein is a general-purpose graphics processing unit including a multiprocessor having a single instruction, multiple thread, SIMT, architecture. The multiprocessor comprises multiple sets of compute units each having a first logic unit configured to perform floating-point operations and a second logic unit configured to perform integer operations, with a thread of the floating-point instruction being executed in parallel with a thread of the integer instruction.

公开(公告)号：US11727246B2

公开(公告)日：2023-08-15

申请号：US16283021

申请日：2019-02-22

Applicant: Intel Corporation

Inventor： Liwei Ma ,  Elmoustapha Ould-Ahmed-Vall ,  Barath Lakshmanan ,  Ben J. Ashbaugh ,  Jingyi Jin ,  Jeremy Bottleson ,  Mike B. Macpherson ,  Kevin Nealis ,  Dhawal Srivastava ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland ,  Xiaoming Chen ,  Anbang Yao ,  Tatiana Shpeisman ,  Altug Koker ,  Abhishek R. Appu

IPC: G06N3/04 ,  G06N3/082 ,  G06N3/063 ,  G06T1/20 ,  G06N3/044 ,  G06N3/045

CPC classification number: G06N3/04 ,  G06N3/063 ,  G06N3/082 ,  G06T1/20 ,  G06N3/044 ,  G06N3/045

Abstract: Embodiments provide systems and methods which facilitate optimization of a convolutional neural network (CNN). One embodiment provides for a non-transitory machine-readable medium storing instructions that cause one or more processors to perform operations comprising processing a trained convolutional neural network (CNN) to generate a processed CNN, the trained CNN having weights in a floating-point format. Processing the trained CNN includes quantizing the weights in the floating-point format to generate weights in an integer format. Quantizing the weights includes generating a quantization table to enable non-uniform quantization of the weights and quantizing the weights from the floating-point format to the integer format using the quantization table. The operations additionally comprise performing an inference operation utilizing the processed CNN with the integer format weights.

公开(公告)号：US11615284B2

公开(公告)日：2023-03-28

申请号：US16468281

申请日：2016-12-22

Applicant: INTEL CORPORATION

Inventor： Liwei Ma ,  Jiqiang Song ,  Hong Zhang

IPC: G06V40/20 ,  G06N3/008 ,  G06N20/00 ,  G06K9/62 ,  G06N3/08

Abstract: A mechanism is described for facilitating transferring of human experiences to autonomous machines. A method of embodiments, as described herein, includes facilitating sensing, by one or more sensors, one or more inputs relating to a user, and evaluating the one or more inputs to capture one or more behavior traits of the user. The method may further include training a neural network model based on the one or more behavior traits, and applying the trained neural network model to a computing device to facilitate the computing device to adopt the one or more behavior traits to behave as the user.

公开(公告)号：US20230061331A1

公开(公告)日：2023-03-02

申请号：US17960611

申请日：2022-10-05

Applicant: Intel Corporation

Inventor： Elmoustapha Ould-Ahmed-Vall ,  Sara S. Baghsorkhi ,  Anbang Yao ,  Kevin Nealis ,  Xiaoming Chen ,  Altug Koker ,  Abhishek R. Appu ,  John C. Weast ,  Mike B. Macpherson ,  Dukhwan Kim ,  Linda L. Hurd ,  Ben J. Ashbaugh ,  Barath Lakshmanan ,  Liwei Ma ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland

IPC: G06T1/20 ,  G06F7/483 ,  G06N3/08 ,  G06F9/30 ,  G06N3/04 ,  G06N3/063 ,  G06F9/50 ,  G06F9/38 ,  G06N20/00

Abstract: One embodiment provides a multi-chip module accelerator usable to execute tensor data processing operations a multi-chip module. The multi-chip module may include a memory stack including multiple memory dies and parallel processor circuitry communicatively coupled to the memory stack. The parallel processor circuitry may include multiprocessor cores to execute matrix multiplication and accumulate operations. The matrix multiplication and accumulate operations may include floating-point operations that are configurable to include two-dimensional matrix multiply and accumulate operations involving inputs that have differing floating-point precisions. The floating-point operations may include a first operation at a first precision and a second operation at a second precision. The first operation may include a multiply having at least one 16-bit floating-point input and the second operation may include an accumulate having a 32-bit floating-point input.

公开(公告)号：US20220327357A1

公开(公告)日：2022-10-13

申请号：US17723074

申请日：2022-04-18

Applicant: Intel Corporation

Inventor： Liwei Ma ,  Nadathur Rajagopalan Satish ,  Jeremy Bottleson ,  Farshad Akhbari ,  Eriko Nurvitadhi ,  Chandrasekaran Sakthivel ,  Barath Lakshmanan ,  Jingyi Jin ,  Justin E. Gottschlich ,  Michael Strickland

IPC: G06N3/04 ,  G06F9/50 ,  G06N3/063 ,  G06N3/08

Abstract: An apparatus to facilitate workload scheduling is disclosed. The apparatus includes one or more clients, one or more processing units to processes workloads received from the one or more clients, including hardware resources and scheduling logic to schedule direct access of the hardware resources to the one or more clients to process the workloads.

公开(公告)号：US20210397925A1

公开(公告)日：2021-12-23

申请号：US17446101

申请日：2021-08-26

Applicant: Intel Corporation

Inventor： Liwei Ma ,  Elmoustapha Ould-Ahmed-Vall ,  Barath Lakshmanan ,  Ben J. Ashbaugh ,  Jingyi Jin ,  Jeremy Bottleson ,  Mike B. Macpherson ,  Kevin Nealis ,  Dhawal Srivastava ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland ,  Xiaoming Chen ,  Anbang Yao ,  Tatiana Shpeisman ,  Altug Koker ,  Abhishek R. Appu

IPC: G06N3/04 ,  G06N3/08 ,  G06N3/063 ,  G06T1/20

Abstract: A library of machine learning primitives is provided to optimize a machine learning model to improve the efficiency of inference operations. In one embodiment a trained convolutional neural network (CNN) model is processed into a trained CNN model via pruning, convolution window optimization, and quantization.