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    SECURELY PROVIDING MULTIPLE WAKE-UP TIME OPTIONS FOR PCI EXPRESS
    12.
    发明公开
    SECURELY PROVIDING MULTIPLE WAKE-UP TIME OPTIONS FOR PCI EXPRESS 审中-公开

    公开(公告)号：EP3671478A1

    公开(公告)日：2020-06-24

    申请号：EP19208489.5

    申请日：2019-11-12

    Applicant: Intel Corporation

    Inventor： LI, Ang ,  TAN, Kuan Hua ,  OOI, Eng Hun

    IPC: G06F13/42

    Abstract: Methods, apparatus, and systems for securely providing multiple wake-up time options for PCI Express (PCIe) devices. Under one approach, Vendor Define Messages (VDMs) are exchanged between a host application layer in a host and a device application layer in a PCIe endpoint device coupled to the host via a PCIe link to effect changes to the L1.2 Substate exit time of a PCIe device. Under another approach, Vendor-Specific Extended Capability (VSEC) structures are exchanged between a host application layer and a device application layer to effect the changes. The VDMs and VSEC structures may also be used to enable a host to read Tpower_on capability information defining power modes supported by a PCIe device. Additionally, VSEC implementations are provided that implement VSEC components in the PCIe device transaction layer or the PCIe device application layer.

    IN-SYSTEM PROVISIONING OF FIRMWARE FOR A HARDWARE PLATFORM
    13.
    发明公开
    IN-SYSTEM PROVISIONING OF FIRMWARE FOR A HARDWARE PLATFORM 审中-公开
    SYSTEMINTERNEN BEREITSTELLUNG VON固件FÜREINE HARDWARE-PLATTFORM

    公开(公告)号：EP3123312A1

    公开(公告)日：2017-02-01

    申请号：EP15769577.6

    申请日：2015-03-27

    Applicant: Intel Corporation

    Inventor： SARANGDHAR, Nitin ,  ROYER, Robert, Jr. ,  OOI, Eng Hun ,  MCFARLANE, Brian ,  KATARIA, Mukesh

    IPC: G06F9/44 ,  G06F21/62

    CPC classification number: G06F21/572 ,  G06F9/4403 ,  G06F9/4406 ,  G06F9/4411 ,  G06F11/1417 ,  G06F21/57 ,  G06F21/575 ,  G06F2212/1052 ,  G06F2221/03 ,  G06F2221/033

    Abstract: A hardware platform includes a nonvolatile storage device that can store system firmware as well as code for the primary operating system for the hardware platform. The hardware platform includes a controller that determines the hardware platform lacks functional firmware to boot the primary operating system from the storage device. The controller accesses a firmware image from an external interface that interfaces a device external to the hardware platform, where the external device is a firmware image source. The controller provisions the firmware from the external device to the storage device and initiates a boot sequence from the provisioned firmware.

    Abstract translation: 硬件平台包括可以存储系统固件的非易失性存储设备以及用于硬件平台的主操作系统的代码。 硬件平台包括一个确定硬件平台的控制器缺乏从存储设备引导主操作系统的功能固件。 控制器从外部接口访问固件映像，该外部接口将硬件平台外部的设备连接到外部设备是固件映像源。 控制器将固件从外部设备提供给存储设备，并从配置的固件启动启动顺序。

    EFFICIENT LOW POWER EXIT SEQUENCE FOR PERIPHERAL DEVICES
    14.
    发明授权
    EFFICIENT LOW POWER EXIT SEQUENCE FOR PERIPHERAL DEVICES 有权
    外围设备的高效低功率出口序列

    公开(公告)号：EP2901245B1

    公开(公告)日：2017-09-27

    申请号：EP13843006.1

    申请日：2013-06-10

    Applicant: Intel Corporation

    Inventor： OOI, Eng Hun

    IPC: G06F1/32 ,  G06F13/00

    CPC classification number: G06F1/3206 ,  G06F1/325 ,  G06F1/3268 ,  Y02D10/154 ,  Y02D50/20

    Abstract: Embodiments of the invention describe methods, apparatuses and systems for providing an efficient low power exit sequence for peripheral devices. In embodiments of the invention, a signal from a host device is transmitted to a SATA peripheral device for exiting a low-power state. An initialization time for OOB transmission and reception logic of the SATA peripheral device is tracked, and a reference time value based on the tracked initialization time is stored. In subsequent transitions from said low-power state, the reference time value for waking a host physical layer is utilized, thereby improving the efficiency of the management and use of said low power state. In some embodiments, the above described tracked initialization comprises a time from a transmission of an OOB signal (from the host to the peripheral device) to receiving an OOB response at the host device from the SATA peripheral device.

    Abstract translation: 本发明的实施例描述了用于为外围设备提供有效的低功率退出序列的方法，装置和系统。 在本发明的实施例中，来自主机设备的信号被传输到SATA外围设备以退出低功率状态。 跟踪SATA外围设备的OOB发送和接收逻辑的初始化时间，并且存储基于跟踪的初始化时间的参考时间值。 在从所述低功率状态的后续转换中，利用用于唤醒主机物理层的参考时间值，由此提高所述低功率状态的管理和使用的效率。 在一些实施例中，上述跟踪初始化包括从OOB信号的传输（从主机到外围设备）到从主机设备接收来自SATA外围设备的OOB响应的时间。

    EFFICIENT LOW POWER EXIT SEQUENCE FOR PERIPHERAL DEVICES
    16.
    发明公开
    EFFICIENT LOW POWER EXIT SEQUENCE FOR PERIPHERAL DEVICES 有权
    高效低功耗终止序列外围设备

    公开(公告)号：EP2901245A1

    公开(公告)日：2015-08-05

    申请号：EP13843006.1

    申请日：2013-06-10

    Applicant: Intel Corporation

    Inventor： OOI, Eng Hun

    IPC: G06F1/32 ,  G06F13/00

    CPC classification number: G06F1/3206 ,  G06F1/325 ,  G06F1/3268 ,  Y02D10/154 ,  Y02D50/20

    Abstract: Embodiments of the invention describe methods, apparatuses and systems for providing an efficient low power exit sequence for peripheral devices. In embodiments of the invention, a signal from a host device is transmitted to a SATA peripheral device for exiting a low-power state. An initialization time for OOB transmission and reception logic of the SATA peripheral device is tracked, and a reference time value based on the tracked initialization time is stored. In subsequent transitions from said low-power state, the reference time value for waking a host physical layer is utilized, thereby improving the efficiency of the management and use of said low power state. In some embodiments, the above described tracked initialization comprises a time from a transmission of an OOB signal (from the host to the peripheral device) to receiving an OOB response at the host device from the SATA peripheral device.

    LOWER-POWER SCRAMBLING WITH IMPROVED SIGNAL INTEGRITY
    20.
    发明公开
    LOWER-POWER SCRAMBLING WITH IMPROVED SIGNAL INTEGRITY 审中-公开
    具有改善的信号完整性的较低功率扰乱

    公开(公告)号：EP3238345A1

    公开(公告)日：2017-11-01

    申请号：EP15873988.8

    申请日：2015-11-23

    Applicant: Intel Corporation

    Inventor： TEOH, Ee Loon ,  OOI, Eng Hun ,  MOZAK, Christopher P. ,  MCFARLANE, Brian R.

    IPC: H03M13/00

    CPC classification number: G06F13/4282 ,  G06F13/1668 ,  G06F13/28 ,  G06F21/79 ,  Y02D10/14 ,  Y02D10/151

    Abstract: An I/O interface supports scrambling, where the scrambling can include nonlinear scrambling of the scrambling code, or dynamic bus inversion of the scrambling code, or selective switching of selected bits of the scrambling code, or a combination of these. The transmitting device includes a scrambler and the receiving device includes a descrambler. Both the scrambler and the descrambler generate a linear feedback scrambling code modified by applying one or more of the techniques mentioned above. The modified scrambling code may cause fewer than half of the scrambled output bits to be toggled with respect to a previous scrambled output. The scrambler applies the modified scrambling code to a signal to transmit. The descrambler applies the modified scrambling code to a received signal.

    Abstract translation: I / O接口支持加扰，其中加扰可以包括加扰码的非线性加扰，或加扰码的动态总线倒置，或加扰码的选定位的选择性切换，或这些的组合。 发送设备包括扰码器，并且接收设备包括解扰器。 扰码器和解扰器都生成通过应用上述一种或多种技术而修改的线性反馈扰码。 修改的扰码可以使得相对于先前的扰码输出来说，少于一半的扰码输出位被切换。 扰码器将修改的扰码应用于要发送的信号。 解扰器将修改的扰码应用于接收的信号。

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