公开(公告)号：US11538806B2

公开(公告)日：2022-12-27

申请号：US16143951

申请日：2018-09-27

Applicant: Intel Corporation

Inventor： Roza Kotlyar ,  Rishabh Mehandru ,  Stephen Cea ,  Biswajeet Guha ,  Dax Crum ,  Tahir Ghani

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/08 ,  H01L29/49

Abstract: Gate-all-around integrated circuit structures having high mobility, and methods of fabricating gate-all-around integrated circuit structures having high mobility, are described. For example, an integrated circuit structure includes a silicon nanowire or nanoribbon. An N-type gate stack is around the silicon nanowire or nanoribbon, the N-type gate stack including a compressively stressing gate electrode. A first N-type epitaxial source or drain structure is at a first end of the silicon nanowire or nanoribbon. A second N-type epitaxial source or drain structure is at a second end of the silicon nanowire or nanoribbon. The silicon nanowire or nanoribbon has a plane between the first N-type epitaxial source or drain structure and the second N-type epitaxial source or drain structure.

公开(公告)号：US11183564B2

公开(公告)日：2021-11-23

申请号：US16015087

申请日：2018-06-21

Applicant: Intel Corporation

Inventor： Nicole K. Thomas ,  Ravi Pillarisetty ,  Payam Amin ,  Roza Kotlyar ,  Patrick H. Keys ,  Hubert C. George ,  Kanwaljit Singh ,  James S. Clarke ,  David J. Michalak ,  Lester Lampert ,  Zachary R. Yoscovits ,  Roman Caudillo ,  Jeanette M. Roberts

IPC: H01L29/12 ,  H01L29/66 ,  H01L29/76 ,  H01L29/423 ,  H01L29/165 ,  H01L27/18 ,  H01L21/8234 ,  H01L29/10 ,  G06N10/00 ,  H01L39/14 ,  H01L29/06 ,  B82Y10/00 ,  H01L29/82 ,  H01L29/40 ,  H01L21/321 ,  H01L21/02 ,  H01L29/778 ,  H01L29/43

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer and a barrier layer; a first gate metal above the quantum well stack, wherein the barrier layer is between the first gate metal and the quantum well layer; and a second gate metal above the quantum well stack, wherein the barrier layer is between the second gate metal and the quantum well layer, and a material structure of the second gate metal is different from a material structure of the first gate metal.

公开(公告)号：US20190043951A1

公开(公告)日：2019-02-07

申请号：US16015087

申请日：2018-06-21

Applicant: Intel Corporation

Inventor： Nicole K. Thomas ,  Ravi Pillarisetty ,  Payam Amin ,  Roza Kotlyar ,  Patrick H. Keys ,  Hubert C. George ,  Kanwaljit Singh ,  James S. Clarke ,  David J. Michalak ,  Lester Lampert ,  Zachary R. Yoscovits ,  Roman Caudillo ,  Jeanette M. Roberts

IPC: H01L29/12 ,  H01L29/10 ,  H01L29/423 ,  H01L29/165 ,  H01L21/02 ,  H01L29/66 ,  H01L29/778 ,  G06N99/00

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer and a barrier layer; a first gate metal above the quantum well stack, wherein the barrier layer is between the first gate metal and the quantum well layer; and a second gate metal above the quantum well stack, wherein the barrier layer is between the second gate metal and the quantum well layer, and a material structure of the second gate metal is different from a material structure of the first gate metal.

公开(公告)号：US10128356B2

公开(公告)日：2018-11-13

申请号：US15118843

申请日：2014-03-27

Applicant: Intel Corporation

Inventor： Uygar E. Avci ,  Roza Kotlyar ,  Ian A. Young

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/18 ,  H01L29/78 ,  H01L29/88 ,  H01L29/739 ,  G06F3/041 ,  H01L23/66 ,  H01L29/786 ,  H01L29/423 ,  H01L29/165 ,  H01L29/205

Abstract: Tunneling field effect transistors (TFETs) are described herein. In an example, a TFET includes a pocket disposed near a junction of a source region, wherein the pocket region is formed from a material having lower percentage of one type of atom than percentage of the one type of atom in source, channel, and drain regions.

公开(公告)号：US10109711B2

公开(公告)日：2018-10-23

申请号：US15024348

申请日：2013-12-16

Applicant: INTEL CORPORATION

Inventor： Stephen M Cea ,  Roza Kotlyar ,  Harold W Kennel ,  Anand S Murthy ,  Glenn A Glass ,  Kelin J Kuhn ,  Tahir Ghani

IPC: H01L29/10 ,  H01L27/092 ,  H01L29/161 ,  H01L29/04 ,  H01L29/66 ,  H01L29/778 ,  H01L29/165 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12

Abstract: Techniques and methods related to strained NMOS and PMOS devices without relaxed substrates, systems incorporating such semiconductor devices, and methods therefor may include a semiconductor device that may have both n-type and p-type semiconductor bodies. Both types of semiconductor bodies may be formed from an initially strained semiconductor material such as silicon germanium. A silicon cladding layer may then be provided at least over or on the n-type semiconductor body. In one example, a lower portion of the semiconductor bodies is formed by a Si extension of the wafer or substrate. By one approach, an upper portion of the semiconductor bodies, formed of the strained SiGe, may be formed by blanket depositing the strained SiGe layer on the Si wafer, and then etching through the SiGe layer and into the Si wafer to form the semiconductor bodies or fins with the lower and upper portions.

公开(公告)号：US09972686B2

公开(公告)日：2018-05-15

申请号：US15121745

申请日：2014-03-27

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Van H. Le ,  Willy Rachmady ,  Roza Kotlyar ,  Marko Radosavljevic ,  Han Wui Then ,  Sansaptak Dasgupta ,  Gilbert Dewey ,  Benjamin Chu-Kung ,  Jack T. Kavalieros

IPC: H01L21/70 ,  H01L29/161 ,  H01L27/11 ,  H01L29/78 ,  H01L29/165 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L29/161 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Techniques related to transistors and integrated circuits having germanium tin, systems incorporating such transistors, and methods for forming them are discussed. Such transistors include a channel region that comprises a germanium tin portion of a fin such that the fin includes a buffer layer disposed over a substrate and the germanium tin portion disposed over the buffer layer.

公开(公告)号：US20170133493A1

公开(公告)日：2017-05-11

申请号：US15410548

申请日：2017-01-19

Applicant: Intel Corporation

Inventor： Roza Kotlyar ,  Stephen M. Cea ,  Gilbert Dewey ,  Benjamin Chu-Kung ,  Uygar E. Avci ,  Rafael Rios ,  Anurag Chaudhry ,  Thomas D. Linton, JR. ,  Ian A. Young ,  Kelin J. Kuhn

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/20 ,  H01L29/423 ,  H01L29/161 ,  H01L29/10 ,  H01L29/786 ,  H01L29/165

CPC classification number: H01L29/66977 ,  H01L27/092 ,  H01L29/045 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/20 ,  H01L29/24 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/7391 ,  H01L29/7842 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78642 ,  H01L29/78684 ,  H01L29/78696

Abstract: Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs are described. For example, a tunneling field effect transistor (TFET) includes a homojunction active region disposed above a substrate. The homojunction active region includes a relaxed Ge or GeSn body having an undoped channel region therein. The homojunction active region also includes doped source and drain regions disposed in the relaxed Ge or GeSn body, on either side of the channel region. The TFET also includes a gate stack disposed on the channel region, between the source and drain regions. The gate stack includes a gate dielectric portion and gate electrode portion.

公开(公告)号：US20160190282A1

公开(公告)日：2016-06-30

申请号：US15062007

申请日：2016-03-04

Applicant: Intel Corporation

Inventor： Brian S. Doyle ,  Uday Shah ,  Roza Kotlyar ,  Charles C. Kuo

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/205 ,  H01L29/165 ,  H01L21/02 ,  H01L21/306 ,  H01L29/10

CPC classification number: H01L29/66666 ,  H01L21/02532 ,  H01L21/30604 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/201 ,  H01L29/205 ,  H01L29/4983 ,  H01L29/66356 ,  H01L29/66363 ,  H01L29/7391 ,  H01L29/749 ,  H01L29/7827 ,  H01L29/7848

Abstract: Vertical transistor devices are described. For example, in one embodiment, a vertical transistor device includes an epitaxial source semiconductor region disposed on a substrate, an epitaxial channel semiconductor region disposed on the source semiconductor region, an epitaxial drain semiconductor region disposed on the channel semiconductor region, and a gate electrode region surrounding sidewalls of the semiconductor channel region. A composition of at least one of the semiconductor regions varies along a longitudinal axis that is perpendicular with respect to a surface of the substrate.

公开(公告)号：US09293560B2

公开(公告)日：2016-03-22

申请号：US14534088

申请日：2014-11-05

Applicant: Intel Corporation

Inventor： Brian S. Doyle ,  Roza Kotlyar ,  Uday Shah ,  Charles C. Kuo

IPC: H01L21/336 ,  H01L29/66 ,  B82Y10/00 ,  H01L29/423 ,  H01L29/775 ,  H01L29/06 ,  H01L21/02 ,  H01L29/16

CPC classification number: H01L29/7827 ,  B82Y10/00 ,  H01L21/0237 ,  H01L21/02636 ,  H01L29/0669 ,  H01L29/0676 ,  H01L29/16 ,  H01L29/165 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/66431 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/775 ,  Y10S977/762

Abstract: Vertically oriented nanowire transistors including semiconductor layers or gate electrodes having compositions that vary over a length of the transistor. In embodiments, transistor channel regions are compositionally graded, or layered along a length of the channel to induce strain, and/or include a high mobility injection layer. In embodiments, a gate electrode stack including a plurality of gate electrode materials is deposited to modulate the gate electrode work function along the gate length.

Abstract translation: 垂直取向的纳米线晶体管包括具有在晶体管的长度上变化的组成的半导体层或栅电极。 在实施例中，晶体管沟道区域沿着沟道的长度成分地分级或分层以诱导应变，和/或包括高迁移率注入层。 在实施例中，沉积包括多个栅电极材料的栅极电极堆叠以沿着栅极长度调制栅电极功函数。

公开(公告)号：US10665770B2

公开(公告)日：2020-05-26

申请号：US15913799

申请日：2018-03-06

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Kanwaljit Singh ,  Patrick H. Keys ,  Roman Caudillo ,  Hubert C. George ,  Zachary R. Yoscovits ,  Nicole K. Thomas ,  James S. Clarke ,  Roza Kotlyar ,  Payam Amin ,  Jeanette M. Roberts

IPC: H01L39/22 ,  H01L39/02 ,  H01L39/24 ,  H01L39/04 ,  G06N10/00 ,  H01L29/12 ,  H01L27/18 ,  H01L29/66 ,  B82Y10/00 ,  H01L39/14 ,  H01L29/76 ,  H01L29/423 ,  H01L29/06 ,  H01L29/16 ,  H01L21/8234

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a base; a fin extending away from the base, wherein the fin includes a quantum well layer; a gate above the fin; and a material on side faces of the fin; wherein the fin has a width between its side faces, and the fin is strained in the direction of the width.