公开(公告)号：US11437504B2

公开(公告)日：2022-09-06

申请号：US16643926

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Sansaptak Dasgupta ,  Marko Radosavljevic

IPC: H01L29/778 ,  H01L29/66 ,  H01L27/06 ,  H01L27/092 ,  H01L29/20

Abstract: Group III-N transistors of complementary conductivity type employing two polarization junctions of complementary type. Each III-N polarization junction may include two III-N material layers having opposite crystal polarities. The opposing polarities may induce a two-dimensional charge sheet within each of the two III-N material layers. Opposing crystal polarities may be induced through introduction of an intervening layer between two III-N material layers. A III-N heterostructure may include two III-N polarization junctions. A 2D electron gas (2DEG) is induced at a first polarization junction and a 2D hole gas (2DHG) is induced at the second polarization junction. Transistors of complementary type may utilize a separate one of the polarization junctions, enabling III-N transistors to implement CMOS circuitry.

公开(公告)号：US11387329B2

公开(公告)日：2022-07-12

申请号：US16147275

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta ,  Paul Fischer ,  Walid Hafez

IPC: H01L29/20 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/51 ,  H01L27/088 ,  H01L29/778

Abstract: Transistor structures including a fin structure having multiple graded III-N material layers with polarization layers therebetween, integrated circuits including such transistor structures, and methods for forming the transistor structures are discussed. The transistor structures further include a source, a drain, and a gate coupled to the fin structure. The fin structure provides a multi-gate multi-nanowire confined transistor architecture.

公开(公告)号：US11387327B2

公开(公告)日：2022-07-12

申请号：US16144946

申请日：2018-09-27

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Marko Radosavljevic ,  Han Wui Then ,  Paul Fischer ,  Walid Hafez

IPC: H01L29/20 ,  H01L21/285 ,  H01L29/778 ,  H01L21/033 ,  H01L21/768 ,  H01L29/49 ,  H01L29/51 ,  H01L21/321

Abstract: A transistor includes a polarization layer above a channel layer including a first III-Nitride (III-N) material, a gate electrode above the polarization layer, a source structure and a drain structure on opposite sides of the gate electrode, where the source structure and a drain structure each include a second III-N material. The transistor further includes a silicide on at least a portion of the source structure or the drain structure. A contact is coupled through the silicide to the source or drain structure.

公开(公告)号：US20220172996A1

公开(公告)日：2022-06-02

申请号：US17675961

申请日：2022-02-18

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta

IPC: H01L21/8252 ,  H01L27/06 ,  H01L29/04 ,  H01L29/267 ,  H01L29/66 ,  H01L29/73 ,  H01L29/778

Abstract: Techniques related to III-N transistors having improved performance, systems incorporating such transistors, and methods for forming them are discussed. Such transistors include first and second crystalline III-N material layers separated by an intervening layer other than a III-N material such that the first crystalline III-N material layer has a first crystal orientation that is inverted with respect to a second crystal orientation of the second crystalline III-N material layer.

公开(公告)号：US11335800B2

公开(公告)日：2022-05-17

申请号：US16016411

申请日：2018-06-22

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta ,  Paul Fischer ,  Walid Hafez

IPC: H01L29/20 ,  H01L29/778 ,  H01L29/205 ,  H01L21/02 ,  H01L29/66 ,  H01L29/08 ,  H01L29/423 ,  H01L29/49 ,  H01L27/088 ,  H01L21/8252

Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate, an epitaxial layer on the substrate, a semiconductor interlayer on top of the epitaxial layer, a gate conductor above the semiconductor interlayer, a gate insulator on the bottom and sides of the gate conductor and contacting the top surface of the semiconductor interlayer, a source region extending into the epitaxial layer, and a drain region extending into the epitaxial layer. The semiconductor device also includes a first polarization layer on the semiconductor interlayer between the source region and the gate conductor and a second polarization layer on the semiconductor interlayer between the drain region and the gate conductor.

公开(公告)号：US20220122842A1

公开(公告)日：2022-04-21

申请号：US17563968

申请日：2021-12-28

Applicant: Intel Corporation

Inventor： Khaled Ahmed ,  Anup Pancholi ,  John Heck ,  Thomas Sounart ,  Harel Frish ,  Sansaptak Dasgupta

IPC: H01L21/02 ,  H01L21/8234 ,  H01L21/8222

Abstract: A device includes a layer including a first III-Nitride (III-N) material, a channel layer including a second III-N material, a release layer including nitrogen and a transition metal, where the release layer is between the first III-N material and the second III-N material. The device further includes a polarization layer including a third III-N material above the release layer, a gate structure above the polarization layer, a source structure and a drain structure on opposite sides of the gate structure where the source structure and the drain structure each include a fourth III-N material. The device further includes a source contact on the source structure and a drain contact on the drain structure.

公开(公告)号：US11233053B2

公开(公告)日：2022-01-25

申请号：US16643827

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Marko Radosavljevic ,  Han Wui Then ,  Sansaptak Dasgupta

IPC: H01L27/092 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/20 ,  H01L29/66 ,  H01L29/78

Abstract: A device including a III-N material is described. In an example, the device has a terminal structure with a central body and a first plurality of fins, and a second plurality of fins, opposite the first plurality of fins. A polarization charge inducing layer including a III-N material in the terminal structure. A gate electrode is disposed above and on a portion of the polarization charge inducing layer. A source structure is on the polarization charge inducing layer and on sidewalls of the first plurality of fins. A drain structure is on the polarization charge inducing layer and on sidewalls of the second plurality of fins. The device further includes a source structure and a drain structure on opposite sides of the gate electrode and a source contact on the source structure and a drain contact on the drain structure.

公开(公告)号：US11222982B2

公开(公告)日：2022-01-11

申请号：US16321356

申请日：2016-09-29

Applicant: Intel Corporation

Inventor： Marko Radosavljevic ,  Sansaptak Dasgupta ,  Han Wui Then

IPC: H01L21/8258 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/06 ,  H01L29/66 ,  H01L29/10 ,  H01L29/20

Abstract: Methods and apparatus to form silicon-based transistors on group III-nitride materials using aspect ratio trapping are disclosed. An example integrated circuit includes a group III-nitride substrate and a fin of silicon formed on the group III-nitride substrate. The integrated circuit further includes a first transistor formed on the fin of silicon and a second transistor formed on the group III-nitride substrate.

公开(公告)号：US20210375620A1

公开(公告)日：2021-12-02

申请号：US16890937

申请日：2020-06-02

Applicant: Intel Corporation

Inventor： Khaled Ahmed ,  Anup Pancholi ,  John Heck ,  Thomas Sounart ,  Harel Frish ,  Sansaptak Dasgupta

IPC: H01L21/02 ,  H01L21/8222 ,  H01L21/8234

Abstract: A device includes a layer including a first III-Nitride (III-N) material, a channel layer including a second III-N material, a release layer including nitrogen and a transition metal, where the release layer is between the first III-N material and the second III-N material. The device further includes a polarization layer including a third III-N material above the release layer, a gate structure above the polarization layer, a source structure and a drain structure on opposite sides of the gate structure where the source structure and the drain structure each include a fourth III-N material. The device further includes a source contact on the source structure and a drain contact on the drain structure.

公开(公告)号：US11107764B2

公开(公告)日：2021-08-31

申请号：US16629936

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta ,  Tristan A. Tronic ,  Rajat K. Paul

IPC: H01L23/525 ,  H01L29/20 ,  H01L29/78

Abstract: Group III-V semiconductor fuses and their methods of fabrication are described. In an example, a fuse includes a gallium nitride layer on a substrate. An oxide layer is disposed in a trench in the gallium nitride layer. A first contact is on the gallium nitride layer on a first side of the trench, the first contact comprising indium, gallium and nitrogen. A second contact is on the gallium nitride layer on a second side of the trench, the second side opposite the first side, the second contact comprising indium, gallium and nitrogen. A filament is over the oxide layer in the trench, the filament coupled to the first contact and to the second contact wherein the filament comprises indium, gallium and nitrogen.