公开(公告)号：US20200210238A1

公开(公告)日：2020-07-02

申请号：US16726341

申请日：2019-12-24

Applicant: Intel Corporation

Inventor： Abhishek R Appu ,  Altug Koker ,  Balaji Vembu ,  Joydeep Ray ,  Kamal Sinha ,  Prasoonkumar Surti ,  Kiran C. Veernapu ,  Subramaniam Maiyuran ,  Sanjeev S. Jahagirdar ,  Eric J. Asperheim ,  Guei-Yuan Lueh ,  David Puffer ,  Wenyin Fu ,  Nikos Kaburlasos ,  Bhushan M. Borole ,  Josh B. Mastronarde ,  Linda L. Hurd ,  Travis T. Schluessler ,  Tomasz Janczak ,  Abhishek Venkatesh ,  Kai Xiao ,  Slawomir Grajewski

IPC: G06F9/50 ,  G06T15/00 ,  G06T1/60 ,  G06T1/20 ,  G06F9/48 ,  G06F1/329

Abstract: In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.

公开(公告)号：US20180300933A1

公开(公告)日：2018-10-18

申请号：US15489177

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Devan Burke ,  Adam T. Lake ,  Jeffery S. Boles ,  John H. Feit ,  Karthik Vaidyanathan ,  Abhishek R. Appu ,  Joydeep Ray ,  Subramaniam Maiyuran ,  Altug Koker ,  Balaji Vembu ,  Murali Ramadoss ,  Prasoonkumar Surti ,  Eric J. Hoekstra ,  Gabor Liktor ,  Jonathan Kennedy ,  Slawomir Grajewski ,  Elmoustapha Ould-Ahmed-Vall

IPC: G06T15/00

Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The system may include one or more of a draw call re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more draw calls, a workload re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more work items in an order independent mode, a queue primitive included in at least one of the two or more draw calls to define a producer stage and a consumer stage, and an order-independent executor communicatively coupled to the application processor and the graphics subsystem to provide tile-based order independent execution of a compute stage. Other embodiments are disclosed and claimed.

公开(公告)号：US11762696B2

公开(公告)日：2023-09-19

申请号：US17520583

申请日：2021-11-05

Applicant: Intel Corporation

Inventor： Abhishek R Appu ,  Altug Koker ,  Balaji Vembu ,  Joydeep Ray ,  Kamal Sinha ,  Prasoonkumar Surti ,  Kiran C. Veernapu ,  Subramaniam Maiyuran ,  Sanjeev S. Jahagirdar ,  Eric J. Asperheim ,  Guei-Yuan Lueh ,  David Puffer ,  Wenyin Fu ,  Nikos Kaburlasos ,  Bhushan M. Borole ,  Josh B. Mastronarde ,  Linda L. Hurd ,  Travis T. Schluessler ,  Tomasz Janczak ,  Abhishek Venkatesh ,  Kai Xiao ,  Slawomir Grajewski

IPC: G06F9/50 ,  G06F1/329 ,  G06F9/48 ,  G06T1/20 ,  G06T1/60 ,  G06T15/00

CPC classification number: G06F9/5016 ,  G06F1/329 ,  G06F9/4893 ,  G06F9/5044 ,  G06T1/20 ,  G06T1/60 ,  G06T15/005 ,  G06T2200/28 ,  Y02D10/00

Abstract: In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.

公开(公告)号：US20220262059A1

公开(公告)日：2022-08-18

申请号：US17591166

申请日：2022-02-02

Applicant: Intel Corporation

Inventor： Devan Burke ,  Adam T. Lake ,  Jeffery S. Boles ,  John H. Feit ,  Karthik Vaidyanathan ,  Abhishek R. Appu ,  Joydeep Ray ,  Subramaniam Maiyuran ,  Altug Koker ,  Balaji Vembu ,  Murali Ramadoss ,  Prasoonkumar Surti ,  Eric J. Hoekstra ,  Gabor Liktor ,  Jonathan Kennedy ,  Slawomir Grajewski ,  Elmoustapha Ould-Ahmed-Vall

IPC: G06T15/00 ,  G06F9/48

Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The system may include one or more of a draw call re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more draw calls, a workload re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more work items in an order independent mode, a queue primitive included in at least one of the two or more draw calls to define a producer stage and a consumer stage, and an order-independent executor communicatively coupled to the application processor and the graphics subsystem to provide tile-based order independent execution of a compute stage. Other embodiments are disclosed and claimed.

公开(公告)号：US20220076480A1

公开(公告)日：2022-03-10

申请号：US17478161

申请日：2021-09-17

Applicant: Intel Corporation

Inventor： Jonathan Kennedy ,  Gabor Liktor ,  Jeffery S. Boles ,  Slawomir Grajewski ,  Balaji Vembu ,  Travis T. Schluessler ,  Abhishek R. Appu ,  Ankur N. Shah ,  Joydeep Ray ,  Altug Koker ,  Jacek Kwiatkowski

IPC: G06T15/00 ,  A63F13/355

Abstract: Systems, apparatuses, and methods may provide for technology to process graphics data in a virtual gaming environment. The technology may identify, from graphics data in a graphics application, redundant graphics calculations relating to common frame characteristics of one or more graphical scenes to be shared between client game devices of a plurality of users and calculate, in response to the identified redundant graphics calculations, frame characteristics relating to the one or more graphical scenes. Additionally, the technology may send, over a computer network, the calculation of the frame characteristics to the client game devices.

公开(公告)号：US10733692B2

公开(公告)日：2020-08-04

申请号：US16185988

申请日：2018-11-09

Applicant: Intel Corporation

Inventor： Slawomir Grajewski ,  Jason Surprise ,  Zack Waters ,  Mike Apodaca

IPC: G06T1/60 ,  G06T1/20

Abstract: Apparatus and method for resilient interface for updating a graphics processor. For example, one embodiment of an apparatus comprises a graphics processor; and a configuration memory of the graphics processor to be subdivided into a plurality of configuration regions associated with a corresponding plurality of graphics pipeline stages and/or functional units, wherein a host processor executing a graphics driver is to submit a graphics processor configuration update to a command buffer, the graphics processor configuration update including at least one logical memory address associated with a logical view of the configuration memory and configuration data to be used to modify at least one configuration region associated with the at least one logical memory address, and wherein the logical memory address is to be used to identify a corresponding physical memory address for at least one configuration region corresponding to at least one of the graphics pipeline stages and/or functional units, the at least one configuration region to be responsively updated.

公开(公告)号：US20200074714A1

公开(公告)日：2020-03-05

申请号：US16566989

申请日：2019-09-11

Applicant: Intel Corporation

Inventor： Michael Apodaca ,  Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Murali Ramadoss ,  Abhishek Venkatesh ,  Jonathan Kennedy ,  Slawomir Grajewski

IPC: G06T15/00 ,  G06T3/40

Abstract: A computing system to obtain an output includes a multi-plane rendering module includes a renderer receives a plurality of graphical objects to generate one or more image planes of object data, a resampler upscales lower resolution image planes to a higher resolution used by the output image, and a rasterizer combine pixels from a common location in the plurality of image planes after each image plane is upsampled to the higher resolution. The renderer receives one of the graphical objects having a location value along a z-axis of the scene, determines which of a plurality of image planes the graphical objects is located using the z-axis location for the graphical object, each of the planes possess a corresponding image resolution, and renders the graphical object into the image plane at the image resolution corresponding determined image plane.

公开(公告)号：US20190259128A1

公开(公告)日：2019-08-22

申请号：US16256441

申请日：2019-01-24

Applicant: Intel Corporation

Inventor： Abhishek Venkatesh ,  Prasoonkumar Surti ,  Slawomir Grajewski ,  Louis Feng ,  Kai Xiao ,  Tomasz Janczak ,  Devan Burke ,  Travis T. Schluessler

IPC: G06T1/20 ,  G06T1/60

Abstract: An embodiment of a graphics apparatus may include a tile candidate identifier to determine if a compute kernel is a tile candidate, and a compute kernel tiler communicatively coupled to the tile candidate identifier to tile the compute kernel if the compute kernel is determined to be a tile candidate. Other embodiments are disclosed and claimed.

公开(公告)号：US20180300930A1

公开(公告)日：2018-10-18

申请号：US15488824

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Jonathan Kennedy ,  Gabor Liktor ,  Jeffery S. Boles ,  Slawomir Grajewski ,  Balaji Vembu ,  Travis T. Schluessler ,  Abhishek R. Appu ,  Ankur N. Shah ,  Joydeep Ray ,  Altug Koker ,  Jacek Kwiatkowski

IPC: G06T15/00 ,  A63F13/53

CPC classification number: G06T15/005 ,  A63F13/53 ,  A63F2300/303 ,  A63F2300/66

Abstract: Systems, apparatuses, and methods may provide for technology to process graphics data in a virtual gaming environment. The technology may identify, from graphics data in a graphics application, redundant graphics calculations relating to common frame characteristics of one or more graphical scenes to be shared between client game devices of a plurality of users and calculate, in response to the identified redundant graphics calculations, frame characteristics relating to the one or more graphical scenes. Additionally, the technology may send, over a computer network, the calculation of the frame characteristics to the client game devices.

公开(公告)号：US20180286106A1

公开(公告)日：2018-10-04

申请号：US15477028

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Michael Apodaca ,  Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Murali Ramadoss ,  Abhishek Venkatesh ,  Jonathan Kennedy ,  Slawomir Grajewski

IPC: G06T15/20 ,  G06T15/00 ,  G06T7/50 ,  G06T7/70 ,  G06T1/20 ,  G06T3/40

Abstract: A computing system to obtain an output includes a multi-plane rendering module includes a renderer receives a plurality of graphical objects to generate one or more image planes of object data, a resampler upscales lower resolution image planes to a higher resolution used by the output image, and a rasterizer combine pixels from a common location in the plurality of image planes after each image plane is upsampled to the higher resolution. The renderer receives one of the graphical objects having a location value along a z-axis of the scene, determines which of a plurality of image planes the graphical objects is located using the z-axis location for the graphical object, each of the planes possess a corresponding image resolution, and renders the graphical object into the image plane at the image resolution corresponding determined image plane.