公开(公告)号：US20190042432A1

公开(公告)日：2019-02-07

申请号：US15992557

申请日：2018-05-30

Applicant: Intel Corporation

Inventor： Abhishek Khade ,  Patrick Lu ,  Francesc Guim Bernat

IPC: G06F12/0846

Abstract: There is disclosed in one example a computing apparatus, including: a cache; a caching agent (CA); an integrated input/output (IIO) block to provide a cache coherent interface to a peripheral device at a first speed; a core configured to poll an address within the cache via the CA, wherein the address is to receive incoming data from the peripheral device via the IIO, and wherein the core is capable of polling the address at a second speed substantially greater than the first speed; and a hardware uncore agent configured to: identify a collision between the core and the IIO including determining that the core is polling the address at a rate that is determined to interfere with access to the address by the IIO; and throttle the core's access to the address.