公开(公告)号：US20200379530A1

公开(公告)日：2020-12-03

申请号：US16943155

申请日：2020-07-30

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava ,  Rao Jagannadha Rapeta ,  Asad Azam

IPC: G06F1/20 ,  G05B15/02

Abstract: The disclosed embodiments relate to methods, systems and apparatus for dynamic temperature aware functional safety. The disclosed embodiments provide adaptive techniques to track extended dynamic temperature range of a System-on-Chip (SOC) and automatically tune critical IP components of the SOC so that system can operate reliably even at high temperatures. The disclosed embodiments relax the overdesign of the SOC components by reusing existing components such as a ring oscillator to determine temperature at different regions of the SOC. In one embodiment, the disclosed principles use a Calibrated Ring Oscillator (CRO) temperature sensors. The CRO-based temperature sensors provide fast temperature measurement suitable for detecting dynamic temperature ranges and temperature rate of change. The CROs are existing on the SOC and do not require addition of additional sensors.

公开(公告)号：US20190049916A1

公开(公告)日：2019-02-14

申请号：US16155495

申请日：2018-10-09

Applicant: Intel Corporation

Inventor： Nabajit Deka ,  Riccardo Mariani ,  Asad Azam ,  Rajesh Banginwar ,  Wenjun Zhang

IPC: G05B19/042

Abstract: An apparatus of a System on Chip (SoC) to implement a one out of two diagnostics (1oo2D) safety system comprises a memory comprising firmware to provide monitoring of the SoC and a second SoC, and a communication interface to provide cross-monitoring between the SoC and the second SoC. The firmware and the communication interface enable the SoC and the second SoC to implement the 1oo2D safety system without significant hardware or software external to the SoC.

公开(公告)号：US10042412B2

公开(公告)日：2018-08-07

申请号：US14563079

申请日：2014-12-08

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava ,  Jia Jun Lee ,  Asad Azam

IPC: G06F1/32 ,  G06F9/44 ,  G06F13/42 ,  G06F9/4401

Abstract: In some embodiments, provided are circuits and approaches for responding to wake requests over a data bus such as with a USB interface. An interconnect PHY may be placed into an aggressive power reduction mode and in response to a detected wake request on the bus, respond in a sufficient time by keeping at least a portion of a transmitter data path in the PHY powered on during the reduced power mode and responding to the wake request while the PHY re-boots in the background.

公开(公告)号：US20230385070A1

公开(公告)日：2023-11-30

申请号：US18361128

申请日：2023-07-28

Applicant: Intel Corporation

Inventor： Subrata Banik ,  Maulik V. Vaghela ,  Rajaram Regupathy ,  Vincent Zimmer ,  Asad Azam

IPC: G06F9/4401 ,  G06F12/0811 ,  G06F9/30

CPC classification number: G06F9/4403 ,  G06F12/0811 ,  G06F9/30047 ,  G06F9/4406

Abstract: Embodiments are directed to improving boot process for early display initialization and visualization. An embodiment of a system includes a plurality of processor cores; a cache coupled to the plurality of processor cores; and a controller circuit to: initialize a portion of the cache as static memory for hardware initialization code usage before beginning execution of the hardware initialization code after a power on of the hardware processor; and cause initialization of a display device to be performed using the portion of the cache, the initialization of the display device performed independently of initialization of dynamic memory of the hardware processor.

公开(公告)号：US11768691B2

公开(公告)日：2023-09-26

申请号：US17025350

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Subrata Banik ,  Maulik V. Vaghela ,  Rajaram Regupathy ,  Vincent Zimmer ,  Asad Azam

IPC: G06F9/00 ,  G06F15/177 ,  G06F9/4401 ,  G06F12/0811 ,  G06F9/30

CPC classification number: G06F9/4403 ,  G06F9/30047 ,  G06F9/4406 ,  G06F12/0811

Abstract: Embodiments are directed to improving boot process for early display initialization and visualization. An embodiment of a system includes a plurality of processor cores; a cache coupled to the plurality of processor cores; and a controller circuit to: initialize a portion of the cache as static memory for hardware initialization code usage before beginning execution of the hardware initialization code after a power on of the hardware processor; and cause initialization of a display device to be performed using the portion of the cache, the initialization of the display device performed independently of initialization of dynamic memory of the hardware processor.

公开(公告)号：US11506702B2

公开(公告)日：2022-11-22

申请号：US17031107

申请日：2020-09-24

Applicant: Intel Corporation

Inventor： Asad Azam ,  Amit Kumar Srivastava ,  Enrico Carrieri ,  Rajesh Bhaskar

IPC: G01R31/28 ,  G01R31/3177 ,  G01R31/3185 ,  G11C29/32 ,  G11C29/46 ,  G11C29/36 ,  G11C29/08

Abstract: An apparatus of a multi-chip package (MCP) of a functional safety system, comprises a processor to be configured as a master chip in a master-slave arrangement with a slave chip in the MCP, and a memory coupled to the processor to store one or more infield test scan patterns. The processor includes a bock to couple the master chip to the slave chip via a high-speed input/output (IO) interface to retrieve the one or more infield test scan patterns from the memory via the master chip, and to provide the one or more infield test scan patterns to the slave chip via the high-speed IO interface in response to the functional safety system entering an infield test mode.

公开(公告)号：US11250167B2

公开(公告)日：2022-02-15

申请号：US16584110

申请日：2019-09-26

Applicant: Intel Corporation

Inventor： R Selvakumar Raja Gopal ,  Asad Azam

IPC: G06F21/76 ,  H04L9/06 ,  G06F21/60 ,  G01R31/3177 ,  G01R31/317 ,  G06F21/44

Abstract: Various systems and methods for implementing secure system-on-chip (SoC) debugging are described herein. A method of providing secure system-on-a-chip (SoC) debugging, comprises: receiving, from a remote host at a debug companion circuit, a debug initiation request to initiate a debugging session with an SoC associated with the debug companion circuit; encrypting, at the debug companion circuit, a debug handshake command; transmitting the debug handshake command to the SoC from the debug companion circuit, wherein the SoC is configured to authenticate the debug companion circuit, and configure intellectual property (IP) blocks on the SoC to expose debug data to the debug companion circuit in response to authenticating the debug companion circuit; and managing a secure connection with the SoC to obtain debug data and report the debug data to the remote host.

公开(公告)号：US11036266B2

公开(公告)日：2021-06-15

申请号：US16943155

申请日：2020-07-30

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava ,  Rao Jagannadha Rapeta ,  Asad Azam

IPC: G06F1/20 ,  G05B15/02

Abstract: The disclosed embodiments relate to methods, systems and apparatus for dynamic temperature aware functional safety. The disclosed embodiments provide adaptive techniques to track extended dynamic temperature range of a System-on-Chip (SOC) and automatically tune critical IP components of the SOC so that system can operate reliably even at high temperatures. The disclosed embodiments relax the overdesign of the SOC components by reusing existing components such as a ring oscillator to determine temperature at different regions of the SOC. In one embodiment, the disclosed principles use a Calibrated Ring Oscillator (CRO) temperature sensors. The CRO-based temperature sensors provide fast temperature measurement suitable for detecting dynamic temperature ranges and temperature rate of change. The CROs are existing on the SOC and do not require addition of additional sensors.

公开(公告)号：US10928449B2

公开(公告)日：2021-02-23

申请号：US16370993

申请日：2019-03-30

Applicant: Intel Corporation

Inventor： Asad Azam ,  R Selvakumar Raja Gopal ,  Kaitlyn Chen

IPC: G01R31/3187 ,  G06F11/07 ,  G06F11/10 ,  G11C29/00

Abstract: Technologies for built-in self-testing of a memory array using error detection and correction code knowledge include identifying data errors between pseudo random data written to the memory array and the data read back from the memory array and ignoring those data errors determined to be correctable. The data errors may be determined to be correctable if an error corrector circuit can correct those errors or if the number of errors per memory chuck is less than a number of errors correctable by the error correct circuit.

公开(公告)号：US20200379528A1

公开(公告)日：2020-12-03

申请号：US16795919

申请日：2020-02-20

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava ,  Rao Jagannadha Rapeta ,  Asad Azam

IPC: G06F1/20 ,  G05B15/02

Abstract: The disclosed embodiments relate to methods, systems and apparatus for dynamic temperature aware functional safety. The disclosed embodiments provide adaptive techniques to track extended dynamic temperature range of a System-on-Chip (SOC) and automatically tune critical IP components of the SOC so that system can operate reliably even at high temperatures. The disclosed embodiments relax the overdesign of the SOC components by reusing existing components such as a ring oscillator to determine temperature at different regions of the SOC. In one embodiment, the disclosed principles use a Calibrated Ring Oscillator (CRO) temperature sensors. The CRO-based temperature sensors provide fast temperature measurement suitable for detecting dynamic temperature ranges and temperature rate of change. The CROs are existing on the SOC and do not require addition of additional sensors.