公开(公告)号：US20240021562A1

公开(公告)日：2024-01-18

申请号：US18373849

申请日：2023-09-27

Applicant: Intel Corporation

Inventor： Weng Hong TEH ,  Chia-Pin CHIU

IPC: H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L25/16 ,  H01L23/50 ,  H01L25/18

CPC classification number: H01L24/25 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L23/3107 ,  H01L25/16 ,  H01L23/50 ,  H01L25/18 ,  H01L23/3114 ,  H01L2924/15747 ,  H01L2924/12042 ,  H01L23/3128 ,  H01L21/568

Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.

公开(公告)号：US20230314704A1

公开(公告)日：2023-10-05

申请号：US17710709

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Chia-Pin CHIU ,  Kaveh HOSSEINI ,  Omkar KARHADE ,  Tim Tri HOANG

IPC: G02B6/12 ,  H01L25/16

CPC classification number: G02B6/12007 ,  H01L25/167 ,  G02B6/29338

Abstract: Embodiments disclosed herein include an optoelectronic system. In an embodiment, the optoelectronic system comprises a first substrate, a second substrate over the first substrate, and a micro-ring resonator (MRR) over the second substrate. In an embodiment, a heater is integrated into the MRR, a cladding is over the MRR, and a temperature sensor is over the MRR in the cladding.

公开(公告)号：US20230314703A1

公开(公告)日：2023-10-05

申请号：US17710690

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Chia-Pin CHIU ,  Kaveh HOSSEINI ,  Omkar KARHADE

IPC: G02B6/12 ,  G02B6/136

CPC classification number: G02B6/12007 ,  G02B6/136 ,  G02B6/29395

Abstract: Embodiments disclosed herein include optoelectronic systems and methods of forming such systems. In an embodiment, an optoelectronic system comprises a first substrate, a second substrate over the first substrate, and a micro-ring resonator (MRR) over the second substrate. In an embodiment, a heater is integrated into the MRR, a cladding is over the MRR, and an opening is through the first substrate and the second substrate to expose a bottom surface of the MRR.

公开(公告)号：US20230130944A1

公开(公告)日：2023-04-27

申请号：US18089213

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Robert STARKSTON ,  Debendra MALLIK ,  John S. GUZEK ,  Chia-Pin CHIU ,  Deepak KULKARNI ,  Ravi V. MAHAJAN

IPC: H01L23/522 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.

公开(公告)号：US20220199482A1

公开(公告)日：2022-06-23

申请号：US17131671

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Chia-Pin CHIU ,  Zhimin WAN ,  Peng LI ,  Deepak GOYAL

IPC: H01L23/367 ,  H01L23/40 ,  H01L23/38

Abstract: Embodiments disclosed herein include thermoelectric cooling (TEC) dies for multi-chip packages. In an embodiment, a TEC die comprises a glass substrate and an array of N-type semiconductor vias and P-type semiconductor vias through the glass substrate. In an embodiment, conductive traces are over the glass substrate, and individual ones of the conductive traces connect an individual one of the N-type semiconductor vias to an individual one of the P-type semiconductor vias.

公开(公告)号：US20240339428A1

公开(公告)日：2024-10-10

申请号：US18749274

申请日：2024-06-20

Applicant: Intel Corporation

Inventor： Weng Hong TEH ,  Chia-Pin CHIU

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/50 ,  H01L23/538 ,  H01L25/16 ,  H01L25/18

CPC classification number: H01L24/25 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L25/16 ,  H01L25/18 ,  H01L21/568 ,  H01L23/3128 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/2501 ,  H01L2224/2505 ,  H01L2224/2512 ,  H01L2224/255 ,  H01L2224/73209 ,  H01L2224/81005 ,  H01L2224/92133 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/141 ,  H01L2924/1431 ,  H01L2924/1461 ,  H01L2924/15151 ,  H01L2924/15192 ,  H01L2924/15747 ,  H01L2924/18161 ,  H01L2924/18162

Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.

公开(公告)号：US20240061192A1

公开(公告)日：2024-02-22

申请号：US17889233

申请日：2022-08-16

Applicant: Intel Corporation

Inventor： Chia-Pin CHIU ,  Finian ROGERS ,  Tim Tri HOANG ,  Kaveh HOSSEINI ,  Omkar KARHADE

IPC: G02B6/42

CPC classification number: G02B6/425 ,  G02B6/4243

Abstract: Embodiments disclosed herein include electronic packages and methods of forming electronic packages. In an embodiment, the electronic package comprises a package substrate, a die coupled to the package substrate, a photonics integrated circuit (PIC) coupled to the die, and a fiber array unit (FAU) optically coupled to the PIC. In an embodiment, the FAU has a base with a first width and a protrusion with a second width that is smaller than the first width.

公开(公告)号：US20230314849A1

公开(公告)日：2023-10-05

申请号：US17710703

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Chia-Pin CHIU ,  Kaveh HOSSEINI ,  Omkar KARHADE ,  Tim Tri HOANG

IPC: G02F1/01 ,  G02B6/293

CPC classification number: G02F1/0147 ,  G02B6/29395 ,  G02B6/2934 ,  G02F2203/15

Abstract: Embodiments disclosed herein include optoelectronic systems and methods of forming such systems. In an embodiment, an optoelectronic system comprises a first substrate, a second substrate over the first substrate, a micro-ring resonator (MRR) over the second substrate, a heater integrated into the MRR, a cladding over the MRR, an opening through the first substrate and the second substrate to expose a bottom surface of the MRR, and a base spanning across the opening.

公开(公告)号：US20220130789A1

公开(公告)日：2022-04-28

申请号：US17570255

申请日：2022-01-06

Applicant: Intel Corporation

Inventor： Weng Hong TEH ,  Chia-Pin CHIU

IPC: H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L25/16 ,  H01L23/50 ,  H01L25/18

Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.

公开(公告)号：US20220123521A1

公开(公告)日：2022-04-21

申请号：US17076443

申请日：2020-10-21

Applicant: Intel Corporation

Inventor： Chia-Pin CHIU

IPC: H01S5/024

Abstract: Embodiments disclosed herein include dual sided cooling architectures for laser packages. In an embodiment, an electronic package comprises a package substrate, and a laser chip attached to the package substrate. In an embodiment, the laser chip has a first surface and a second surface opposite from the first surface. In an embodiment, an interposer is disposed over the laser chip, where the interposer overhangs an edge of the laser chip. In an embodiment, the electronic package further comprises an interconnect between the interposer and the package substrate.