公开(公告)号：US10884932B2

公开(公告)日：2021-01-05

申请号：US16394829

申请日：2019-04-25

Applicant: Intel Corporation

Inventor： Altug Koker ,  Joydeep Ray ,  James A. Valerio ,  Abhishek R. Appu ,  Vasanth Ranganathan

IPC: G06F12/0842 ,  G06F12/0831 ,  G06F12/0811 ,  G06T1/60 ,  G06F12/0875

Abstract: A mechanism is described for facilitating independent and separate entity-based graphics cache at computing devices. A method of embodiments, as described herein, includes facilitate hosting of a plurality of cache at a plurality of entities associated with a graphics processor, wherein each entity hosts at least one cache, and wherein an entity includes a dual sub-slice (DSS) or a streaming multiprocessor (SM).

公开(公告)号：US10853132B2

公开(公告)日：2020-12-01

申请号：US16379565

申请日：2019-04-09

Applicant: Intel Corporation

Inventor： Altug Koker ,  Joydeep Ray ,  Balaji Vembu ,  James A. Valerio ,  Abhishek R. Appu

IPC: G06F9/48 ,  G06T1/60

Abstract: A mechanism is described for facilitating memory-based software barriers to emulate hardware barriers at graphics processors in computing devices. A method of embodiments, as described herein, includes facilitating converting thread scheduling at a processor from hardware barriers to software barriers, where the software barriers emulate the hardware barriers.

公开(公告)号：US20200327637A1

公开(公告)日：2020-10-15

申请号：US16791482

申请日：2020-02-14

Applicant: Intel Corporation

Inventor： Balaji Vembu ,  Murali Ramadoss ,  Guei-Yuan Lueh ,  Subramaniam M. Maiyuran ,  Abhishek R. Appu ,  Joydeep Ray ,  Altug Koker ,  James A. Valerio ,  Eric J. Hoekstra ,  Arthur D. Hunter, JR.

IPC: G06T1/20 ,  G06T15/04 ,  G06F9/22 ,  G06F9/448

Abstract: An apparatus to facilitate data intelligent dispatching is disclosed. The apparatus includes one or more processing units including a plurality of execution units (EUs) to execute a plurality of processing threads and collection logic to collect statistics data for threads executed at the processing unit during execution of an application, and dispatch logic to dispatch the threads to be executed at a subset of the plurality of EUs during a subsequent execution of the application based on the statistics data.

公开(公告)号：US10657618B2

公开(公告)日：2020-05-19

申请号：US16441499

申请日：2019-06-14

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Altug Koker ,  James A. Valerio ,  David Puffer ,  Abhishek R. Appu ,  Stephen Junkins

IPC: G06T1/60 ,  G06T1/20 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0888

Abstract: One embodiment provides for a general-purpose graphics processing device comprising a general-purpose graphics processing compute block to process a workload including graphics or compute operations, a first cache memory, and a coherency module enable the first cache memory to coherently cache data for the workload, the data stored in memory within a virtual address space, wherein the virtual address space shared with a separate general-purpose processor including a second cache memory that is coherent with the first cache memory.

公开(公告)号：US10657096B2

公开(公告)日：2020-05-19

申请号：US15476987

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  James A. Valerio ,  Altug Koker ,  Abhishek R. Appu ,  Vasanth Ranganathan

IPC: G06F15/80 ,  G06T1/20

Abstract: A shared local memory data crossbar may be implemented in multiple stages. With this approach, the number of multiplexer cells can be reduced by fifty percent (50%) or more in some embodiments.

公开(公告)号：US10565675B2

公开(公告)日：2020-02-18

申请号：US16252379

申请日：2019-01-18

Applicant: Intel Corporation

Inventor： Balaji Vembu ,  Murali Ramadoss ,  Guei-Yuan Lueh ,  Subramaniam M. Maiyuran ,  Abhishek R. Appu ,  Joydeep Ray ,  Altug Koker ,  James A. Valerio ,  Eric J. Hoekstra ,  Arthur D. Hunter, Jr.

IPC: G06T1/20 ,  G06F9/22 ,  G06T15/04 ,  G06F9/448

Abstract: An apparatus to facilitate data intelligent dispatching is disclosed. The apparatus includes one or more processing units including a plurality of execution units (EUs) to execute a plurality of processing threads and collection logic to collect statistics data for threads executed at the processing unit during execution of an application, and dispatch logic to dispatch the threads to be executed at a subset of the plurality of EUs during a subsequent execution of the application based on the statistics data.

公开(公告)号：US10324848B2

公开(公告)日：2019-06-18

申请号：US15483001

申请日：2017-04-10

Applicant: Intel Corporation

Inventor： Altug Koker ,  Joydeep Ray ,  James A. Valerio ,  Abhishek R. Appu ,  Vasanth Ranganathan

IPC: G06F12/0842

Abstract: A mechanism is described for facilitating independent and separate entity-based graphics cache at computing devices. A method of embodiments, as described herein, includes facilitate hosting of a plurality of cache at a plurality of entities associated with a graphics processor, wherein each entity hosts at least one cache, and wherein an entity includes a dual sub-slice (DSS) or a streaming multiprocessor (SM).

公开(公告)号：US10089115B2

公开(公告)日：2018-10-02

申请号：US15203907

申请日：2016-07-07

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Abhishek R. Appu ,  James A. Valerio ,  Bharath Narasimha Swamy

IPC: G06F9/38 ,  G06F13/16 ,  G06F12/0806 ,  G06F12/084

Abstract: One embodiment provides for a graphics processor comprising first logic coupled with a first execution unit, the first logic to receive a first single instruction multiple data (SIMD) message from the first execution unit; second logic coupled with a second execution unit, the second logic to receive a second SIMD message from the second execution unit; and third logic coupled with a bank of shared local memory (SLM), the third logic to receive a first request to access the bank of SLM from the first logic, a second request to access the bank of SLM from the second logic, and in a single access cycle, schedule a read access to a read port for the first request and a write access to a write port for the second request.

公开(公告)号：US11508338B2

公开(公告)日：2022-11-22

申请号：US17062871

申请日：2020-10-05

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Altug Koker ,  Balaji Vembu ,  Murali Ramadoss ,  Guei-Yuan Lueh ,  James A. Valerio ,  Prasoonkumar Surti ,  Abhishek R. Appu ,  Vasanth Ranganathan ,  Kalyan K. Bhiravabhatla ,  Arthur D. Hunter, Jr. ,  Wei-Yu Chen ,  Subramaniam M. Maiyuran

IPC: G09G5/36 ,  G06F12/0875 ,  G06F9/46 ,  G09G5/00 ,  G06F12/084 ,  G06F12/0811

Abstract: A mechanism is described for facilitating using of a shared local memory for register spilling/filling relating to graphics processors at computing devices. A method of embodiments, as described herein, includes reserving one or more spaces of a shared local memory (SLM) to perform one or more of spilling and filling relating to registers associated with a graphics processor of a computing device.

公开(公告)号：US11354768B2

公开(公告)日：2022-06-07

申请号：US16791482

申请日：2020-02-14

Applicant: Intel Corporation

Inventor： Balaji Vembu ,  Murali Ramadoss ,  Guei-Yuan Lueh ,  Subramaniam M. Maiyuran ,  Abhishek R. Appu ,  Joydeep Ray ,  Altug Koker ,  James A. Valerio ,  Eric J. Hoekstra ,  Arthur D. Hunter, Jr.

IPC: G06T1/20 ,  G06T15/04 ,  G06F9/22 ,  G06F9/448

Abstract: An apparatus to facilitate data intelligent dispatching is disclosed. The apparatus includes one or more processing units including a plurality of execution units (EUs) to execute a plurality of processing threads and collection logic to collect statistics data for threads executed at the processing unit during execution of an application, and dispatch logic to dispatch the threads to be executed at a subset of the plurality of EUs during a subsequent execution of the application based on the statistics data.