公开(公告)号：US20190035363A1

公开(公告)日：2019-01-31

申请号：US15858486

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Travis Schluessler ,  Abhishek Venkatesh ,  John Gierach ,  Tomer Bar-On ,  Devan Burke

IPC: G09G5/36 ,  G09G3/00 ,  G09G5/391 ,  G06T15/40 ,  G06T15/20 ,  G06T7/70 ,  G09G5/397

CPC classification number: G09G5/363 ,  G06F3/1446 ,  G06T1/20 ,  G06T1/60 ,  G06T3/0093 ,  G06T7/70 ,  G06T15/005 ,  G06T15/20 ,  G06T15/405 ,  G06T2210/08 ,  G06T2210/36 ,  G06T2210/52 ,  G09G3/003 ,  G09G5/001 ,  G09G5/377 ,  G09G5/391 ,  G09G5/397 ,  G09G2300/026 ,  G09G2320/0252 ,  G09G2330/023 ,  G09G2340/0407 ,  G09G2340/0428 ,  G09G2352/00 ,  G09G2354/00 ,  G09G2360/06 ,  G09G2360/08 ,  G09G2360/121 ,  G09G2360/122

Abstract: Systems, methods and apparatuses may provide for technology to reduce rendering overhead associated with light field displays. The technology may conduct data formatting, re-projection, foveation, tile binning and/or image warping operations with respect to a plurality of display planes in a light field display.

公开(公告)号：US11257182B2

公开(公告)日：2022-02-22

申请号：US16943984

申请日：2020-07-30

Applicant: Intel Corporation

Inventor： John Gierach ,  Abhishek Venkatesh ,  Travis Schluessler ,  Devan Burke ,  Tomer Bar-On ,  Michael Apodaca

IPC: G06T1/20 ,  G06T17/10

Abstract: Embodiments are generally directed to GPU mixed primitive topology type processing. An embodiment of an apparatus includes one or more processor cores; and a memory to store data for graphics processing, wherein the one or more processing cores are to generate in the memory a vertex buffer to store vertex data for a mesh to be rendered and an index buffer to index the vertex data stored in the vertex buffer, the index buffer being structured to include index data for multiple primitive topology types. The one or more processor cores are to process the index data for the plurality of primitive topology types from the index buffer and fetch vertex data from the vertex buffer; and are to set up each primitive topology type of the plurality of primitive topology types for processing in a single draw operation.

公开(公告)号：US20200211511A1

公开(公告)日：2020-07-02

申请号：US16723337

申请日：2019-12-20

Applicant: Intel Corporation

Inventor： Travis Schluessler ,  Abhishek Venkatesh ,  John Gierach ,  Tomer Bar-On ,  Devan Burke

IPC: G09G5/36 ,  G09G5/391 ,  G06T15/40 ,  G06T15/20 ,  G06T7/70 ,  G06T15/00 ,  G09G3/00 ,  G06T1/20 ,  G09G5/00

Abstract: Systems, methods and apparatuses may provide for technology to reduce rendering overhead associated with light field displays. The technology may conduct data formatting, re-projection, foveation, tile binning and/or image warping operations with respect to a plurality of display planes in a light field display.

公开(公告)号：US10540260B2

公开(公告)日：2020-01-21

申请号：US15903393

申请日：2018-02-23

Applicant: Intel Corporation

Inventor： Travis Schluessler ,  Abhishek Venkatesh ,  Elmoustapha Ould-Ahmed-Vall ,  John Gierach ,  Tomer Bar On ,  Devan Burke

IPC: G06F9/44 ,  G06F11/36 ,  G06F9/38 ,  G06T1/20

Abstract: In one example, an apparatus comprises processing circuitry to analyze a program at compile time to determine a set of latency parameters associated with instruction sets implemented to execute the program and select a latency management technique based at least in part on the set of latency parameters associated with instruction sets implemented to execute the program. Other examples may be described and claimed.

公开(公告)号：US10522113B2

公开(公告)日：2019-12-31

申请号：US15858486

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Travis Schluessler ,  Abhishek Venkatesh ,  John Gierach ,  Tomer Bar-On ,  Devan Burke

IPC: G06T15/40 ,  G09G5/36 ,  G09G5/391 ,  G06T15/20 ,  G06T7/70 ,  G06T15/00 ,  G09G3/00 ,  G06T1/20 ,  G09G5/00 ,  G06T3/00 ,  G09G5/397 ,  G06T1/60 ,  G06F3/14 ,  G09G5/377

Abstract: Systems, methods and apparatuses may provide for technology to reduce rendering overhead associated with light field displays. The technology may conduct data formatting, re-projection, foveation, tile binning and/or image warping operations with respect to a plurality of display planes in a light field display.

公开(公告)号：US20190205736A1

公开(公告)日：2019-07-04

申请号：US15858014

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Amit Bleiweiss ,  Abhishek Venkatesh ,  Gokce Keskin ,  John Gierach ,  Oguz Elibol ,  Tomer Bar-On ,  Huma Abidi ,  Devan Burke ,  Jaikrishnan Menon ,  Eriko Nurvitadhi ,  Pruthvi Gowda Thorehosur Appajigowda ,  Travis T. Schluessler ,  Dhawal Srivastava ,  Nishant Patel ,  Anil Thomas

IPC: G06N3/063 ,  G06N5/04 ,  G06N3/04 ,  G06N99/00 ,  G06F9/38 ,  G06N3/08 ,  G06T1/20

CPC classification number: G06N3/063 ,  G06F9/3887 ,  G06N3/04 ,  G06N3/08 ,  G06N5/046 ,  G06N20/00 ,  G06T1/20

Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes a at least one processor to perform operations to implement a neural network and compute logic to accelerate neural network computations.

公开(公告)号：US20250053797A1

公开(公告)日：2025-02-13

申请号：US18812822

申请日：2024-08-22

Applicant: Intel Corporation

Inventor： Amit Bleiweiss ,  Abhishek Venkatesh ,  Gokce Keskin ,  John Gierach ,  Oguz Elibol ,  Tomer Bar-On ,  Huma Abidi ,  Devan Burke ,  Jaikrishnan Menon ,  Eriko Nurvitadhi ,  Pruthvi Gowda Thorehosur Appajigowda ,  Travis T. Schluessler ,  Dhawal Srivastava ,  Nishant Patel ,  Anil Thomas

IPC: G06N3/063 ,  G06F9/38 ,  G06N3/04 ,  G06N3/08 ,  G06N5/046 ,  G06N20/00 ,  G06T1/20

Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes a at least one processor to perform operations to implement a neural network and compute logic to accelerate neural network computations.

公开(公告)号：US12086705B2

公开(公告)日：2024-09-10

申请号：US15858014

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Amit Bleiweiss ,  Abhishek Venkatesh ,  Gokce Keskin ,  John Gierach ,  Oguz Elibol ,  Tomer Bar-On ,  Huma Abidi ,  Devan Burke ,  Jaikrishnan Menon ,  Eriko Nurvitadhi ,  Pruthvi Gowda Thorehosur Appajigowda ,  Travis T. Schluessler ,  Dhawal Srivastava ,  Nishant Patel ,  Anil Thomas

IPC: G06N3/063 ,  G06F9/38 ,  G06N3/04 ,  G06N3/08 ,  G06N5/046 ,  G06N20/00 ,  G06T1/20

CPC classification number: G06N3/063 ,  G06F9/3887 ,  G06N3/04 ,  G06N3/08 ,  G06N5/046 ,  G06N20/00 ,  G06T1/20

Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes a at least one processor to perform operations to implement a neural network and compute logic to accelerate neural network computations.

公开(公告)号：US20220059054A1

公开(公告)日：2022-02-24

申请号：US17461228

申请日：2021-08-30

Applicant: Intel Corporation

Inventor： Travis Schluessler ,  Abhishek Venkatesh ,  John Gierach ,  Tomer Bar-On ,  Devan Burke

IPC: G09G5/36 ,  G09G5/391 ,  G06T15/40 ,  G06T15/20 ,  G06T7/70 ,  G06T15/00 ,  G09G3/00 ,  G06T1/20 ,  G09G5/00

Abstract: Systems, methods and apparatuses may provide for technology to reduce rendering overhead associated with light field displays. The technology may conduct data formatting, re-projection, foveation, tile binning and/or image warping operations with respect to a plurality of display planes in a light field display.

公开(公告)号：US11107444B2

公开(公告)日：2021-08-31

申请号：US16723337

申请日：2019-12-20

Applicant: Intel Corporation

Inventor： Travis Schluessler ,  Abhishek Venkatesh ,  John Gierach ,  Tomer Bar-On ,  Devan Burke

IPC: G06T15/40 ,  G09G5/36 ,  G09G5/391 ,  G06T15/20 ,  G06T7/70 ,  G06T15/00 ,  G09G3/00 ,  G06T1/20 ,  G09G5/00 ,  G06T3/00 ,  G09G5/397 ,  G06T1/60 ,  G09G5/377 ,  G06F3/14

Abstract: Systems, methods and apparatuses may provide for technology to reduce rendering overhead associated with light field displays. The technology may conduct data formatting, re-projection, foveation, tile binning and/or image warping operations with respect to a plurality of display planes in a light field display.