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    DIRECT DIGITAL SYNTHESIS OF SIGNALS USING MAXIMUM LIKELIHOOD BIT-STREAM ENCODING
    11.
    发明申请
    DIRECT DIGITAL SYNTHESIS OF SIGNALS USING MAXIMUM LIKELIHOOD BIT-STREAM ENCODING 审中-公开
    使用最大似然比特流编码的信号的直接数字合成

    公开(公告)号：US20160072647A1

    公开(公告)日：2016-03-10

    申请号：US14944184

    申请日：2015-11-17

    Applicant: Intel Corporation

    Inventor： Kameran Azadet ,  Steven C. Pinault

    IPC: H04L25/03

    CPC classification number: G06F9/3001 ,  G06F5/01 ,  G06F9/30036 ,  G06F17/15 ,  H03F1/0288 ,  H03F1/3241 ,  H03F1/3258 ,  H03F3/189 ,  H03F3/24 ,  H03F2200/336 ,  H03F2201/3209 ,  H03F2201/3212 ,  H03F2201/3224 ,  H03F2201/3233 ,  H03H17/06 ,  H03M3/30 ,  H04B1/0003 ,  H04B1/0475 ,  H04B1/62 ,  H04B2001/0408 ,  H04L1/0054 ,  H04L25/02 ,  H04L25/03 ,  H04L25/03178 ,  H04L25/03216 ,  H04L25/4917 ,  H04L27/2334

    Abstract: Maximum likelihood bit-stream generation and detection techniques are provided using the M-algorithm and Infinite Impulse Response (IIR) filtering. The M-Algorithm is applied to a target input signal X to perform Maximum Likelihood Sequence Estimation on the target input signal X to produce a digital bit stream B, such that after filtering by an IIR filter, the produced digital stream Y produces an error signal satisfying one or more predefined requirements. The predefined requirements comprise, for example, a substantially minimum error. In an exemplary bit detection implementation, the target input signal X comprises an observed analog signal and the produced digital stream Y comprises a digitized output of a receive channel corresponding to a transmitted bit stream. In an exemplary bit stream generation implementation, the target input signal X comprises a desired transmit signal and the produced digital stream Y comprises an estimate of the desired transmit signal.

    Abstract translation: 使用M算法和无限脉冲响应（IIR）滤波提供最大似然比特流生成和检测技术。 将M算法应用于目标输入信号X以对目标输入信号X执行最大似然序列估计，以产生数字比特流B，使得在由IIR滤波器滤波之后，产生的数字流Y产生误差信号 满足一个或多个预定义的要求。 预定义的要求包括例如基本上最小的误差。 在示例性比特检测实现中，目标输入信号X包括观察到的模拟信号，并且所产生的数字流Y包括与发送的比特流相对应的接收信道的数字化输出。 在示例性比特流生成实现中，目标输入信号X包括期望的发射信号，并且所产生的数字流Y包括所需发射信号的估计。

    Method and system for digital equalization of a linear or non-linear system
    12.
    发明授权
    Method and system for digital equalization of a linear or non-linear system 有权

    公开(公告)号：US12206426B2

    公开(公告)日：2025-01-21

    申请号：US17358044

    申请日：2021-06-25

    Applicant: Intel Corporation

    Inventor： Albert Molina ,  Martin Clara ,  Kameran Azadet

    IPC: H03M1/00 ,  H03M1/06 ,  H03M1/10

    Abstract: A system and method for equalization of a linear or non-linear system. The system includes an adder configured to add an analog reference signal and an input signal, a processing system configured to process a sum of the analog reference signal and the input signal, a non-linear equalizer (NLEQ) configured to process an output of the processing system to remove a distortion incurred by the processing system, a calibration circuitry configured to generate a reconstructed reference signal in digital domain based on measurement of the analog reference signal, and generate coefficients for the NLEQ based on the reconstructed reference signal and the output of the processing system, and a subtractor configured to subtract the reconstructed reference signal from an output of the NLEQ. The analog reference signal may be a sinusoid including single or multiple tones of sinusoids. The non-linear system may be an analog-to-digital converter (ADC).

    PROCESSING PIPELINE WITH ZERO LOOP OVERHEAD
    13.
    发明公开
    PROCESSING PIPELINE WITH ZERO LOOP OVERHEAD 审中-公开

    公开(公告)号：US20240345839A1

    公开(公告)日：2024-10-17

    申请号：US18647891

    申请日：2024-04-26

    Applicant: Intel Corporation

    Inventor： Kameran Azadet ,  Jeroen Leijten ,  Joseph Williams

    IPC: G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F9/54

    CPC classification number: G06F9/30036 ,  G06F9/30079 ,  G06F9/3877 ,  G06F9/463 ,  G06F9/546

    Abstract: Techniques are disclosed for reducing or eliminating loop overhead caused by function calls in processors that form part of a pipeline architecture. The processors in the pipeline process data blocks in an iterative fashion, with each processor in the pipeline completing one of several iterations associated with a processing loop for a commonly-executed function. The described techniques leverage the use of message passing for pipelined processors to enable an upstream processor to signal to a downstream processor when processing has been completed, and thus a data block is ready for further processing in accordance with the next loop processing iteration. The described techniques facilitate a zero loop overhead architecture, enable continuous data block processing, and allow the processing pipeline to function indefinitely within the main body of the processing loop associated with the commonly-executed function where efficiency is greatest.

    Processing pipeline with zero loop overhead
    15.
    发明授权
    Processing pipeline with zero loop overhead 有权

    公开(公告)号：US11989554B2

    公开(公告)日：2024-05-21

    申请号：US17131970

    申请日：2020-12-23

    Applicant: Intel Corporation

    Inventor： Kameran Azadet ,  Jeroen Leijten ,  Joseph Williams

    IPC: G06F9/38 ,  G06F9/30 ,  G06F9/46 ,  G06F9/54

    CPC classification number: G06F9/30036 ,  G06F9/30079 ,  G06F9/3877 ,  G06F9/463 ,  G06F9/546

    Abstract: Techniques are disclosed for reducing or eliminating loop overhead caused by function calls in processors that form part of a pipeline architecture. The processors in the pipeline process data blocks in an iterative fashion, with each processor in the pipeline completing one of several iterations associated with a processing loop for a commonly-executed function. The described techniques leverage the use of message passing for pipelined processors to enable an upstream processor to signal to a downstream processor when processing has been completed, and thus a data block is ready for further processing in accordance with the next loop processing iteration. The described techniques facilitate a zero loop overhead architecture, enable continuous data block processing, and allow the processing pipeline to function indefinitely within the main body of the processing loop associated with the commonly-executed function where efficiency is greatest.

    CREST FACTOR REDUCTION USING PEAK CANCELLATION WITHOUT PEAK REGROWTH
    17.
    发明公开
    CREST FACTOR REDUCTION USING PEAK CANCELLATION WITHOUT PEAK REGROWTH 审中-公开

    公开(公告)号：US20240004957A1

    公开(公告)日：2024-01-04

    申请号：US17854095

    申请日：2022-06-30

    Applicant: Intel Corporation

    Inventor： Sunitha Motipalli ,  Kameran Azadet ,  Albert Molina ,  Joseph Othmer ,  Kannan Rajamani

    IPC: G06K9/00

    CPC classification number: G06K9/0053 ,  G06K9/0055

    Abstract: Techniques are disclosed for the use of Crest Factor Reduction (CFR) algorithm that performs oversampling of an input signal and a cancellation pulse, and detects a set of peak samples in the upsampled input signal that exceed a predetermined threshold value. The peak samples are clustered such that a subset of the oversampled signal peaks are used to compute gain factors for the generation of a scaled truncated upsampled cancellation pulse. Several scaled truncated upsampled cancellation pulses are applied in parallel to perform peak cancellation of the highest peak in each cluster as part of an initial peak cancellation process. Any remaining peaks are canceled by iterative gain factors computation process. A final cancellation pulse is then generated by multiplying a cancellation pulse by the computed gain factors.

    Digital-to-analog converter
    19.
    发明授权
    Digital-to-analog converter 有权

    公开(公告)号：US11171663B2

    公开(公告)日：2021-11-09

    申请号：US16833729

    申请日：2020-03-30

    Applicant: Intel Corporation

    Inventor： Daniel Gruber ,  Ramon Sanchez ,  Kameran Azadet ,  Martin Clara

    IPC: H03M1/66 ,  H01P5/10 ,  H04B1/04 ,  H01F19/04 ,  H03H7/38 ,  H03H7/42

    Abstract: A digital-to-analog converter is provided. The digital-to-analog converter includes a first plurality of digital-to-analog converter cells configured to generate a first analog signal. Further, digital-to-analog converter includes a second plurality of digital-to-analog converter cells configured to generate a second analog signal. The first analog signal and the second analog signal form a differential signal pair. Further, the digital-to-analog converter includes a transmission line transformer comprising a first input node coupled to the first plurality of digital-to-analog converter cells, a second input node coupled to the second plurality of digital-to-analog converter cells, and a first output node. The transmission line transformer is configured to present a first impedance at the first and second input nodes and to present a second impedance at the first output node.

    Digital-to-analog conversion system
    20.
    发明授权
    Digital-to-analog conversion system 有权

    公开(公告)号：US10715185B1

    公开(公告)日：2020-07-14

    申请号：US16369317

    申请日：2019-03-29

    Applicant: Intel Corporation

    Inventor： Daniel Gruber ,  Ramon Sanchez ,  Kameran Azadet ,  Martin Clara

    IPC: H04B1/00 ,  H04B1/04 ,  H03M1/66 ,  H04B1/10

    Abstract: A digital-to-analog conversion system is provided. The digital-to-analog conversion system includes a digital-to-analog converter configured to receive a pre-distorted digital signal from a digital circuit, and to generate an analog signal based on the pre-distorted digital signal. Further, the digital-to-analog conversion system includes a feedback loop for providing a digital feedback signal to the digital circuit. The feedback loop includes an analog-to-digital converter configured to generate the digital feedback signal based on the analog signal, and wherein a sample rate of the analog-to-digital converter is lower than a sample rate of the digital-to-analog converter.

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