公开(公告)号：US20230401668A1

公开(公告)日：2023-12-14

申请号：US18456235

申请日：2023-08-25

Applicant: Intel Corporation

Inventor： Elmoustapha Ould-Ahmed-Vall ,  Sara S. Baghsorkhi ,  Anbang Yao ,  Kevin Nealis ,  Xiaoming Chen ,  Altug Koker ,  Abhishek R. Appu ,  John C. Weast ,  Mike B. Macpherson ,  Dukhwan Kim ,  Linda L. Hurd ,  Ben J. Ashbaugh ,  Barath Lakshmanan ,  Liwei Ma ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland

IPC: G06T1/20 ,  G06F7/483 ,  G06N3/084 ,  G06F9/30 ,  G06N3/063 ,  G06F9/50 ,  G06F9/38 ,  G06N3/044 ,  G06N3/045 ,  G06N20/00

CPC classification number: G06T1/20 ,  G06F7/483 ,  G06N3/084 ,  G06F9/30185 ,  G06F9/30014 ,  G06N3/063 ,  G06F9/5044 ,  G06F9/3863 ,  G06N3/044 ,  G06N3/045 ,  G06N20/00 ,  G06F3/14

Abstract: One embodiment provides a general-purpose graphics processing unit comprising a dynamic precision floating-point unit including a control unit having precision tracking hardware logic to track an available number of bits of precision for computed data relative to a target precision, wherein the dynamic precision floating-point unit includes computational logic to output data at multiple precisions.

公开(公告)号：US11580361B2

公开(公告)日：2023-02-14

申请号：US15494826

申请日：2017-04-24

Applicant: Intel Corporation

Inventor： Gokcen Cilingir ,  Elmoustapha Ould-Ahmed-Vall ,  Rajkishore Barik ,  Kevin Nealis ,  Xiaoming Chen ,  Justin E. Gottschlich ,  Prasoonkumar Surti ,  Chandrasekaran Sakthivel ,  Abhishek Appu ,  John C. Weast ,  Sara S. Baghsorkhi ,  Barnan Das ,  Narayan Biswal ,  Stanley J. Baran ,  Nilesh V. Shah ,  Archie Sharma ,  Mayuresh M. Varerkar

IPC: G06N3/08 ,  G06N3/04 ,  G06F9/38 ,  G06N3/063 ,  G06F9/30 ,  G06T1/20 ,  G06N3/084

Abstract: An apparatus to facilitate neural network (NN) training is disclosed. The apparatus includes training logic to receive one or more network constraints and train the NN by automatically determining a best network layout and parameters based on the network constraints.

公开(公告)号：US20220391679A1

公开(公告)日：2022-12-08

申请号：US17886055

申请日：2022-08-11

Applicant: Intel Corporation

Inventor： Rajkishore Barik ,  Elmoustapha Ould-Ahmed-Vall ,  Xiaoming Chen ,  Dhawal Srivastava ,  Anbang Yao ,  Kevin Nealis ,  Eriko Nurvitadhi ,  Sara S. Baghsorkhi ,  Balaji Vembu ,  Tatiana Shpeisman ,  Ping T. Tang

IPC: G06N3/063 ,  G06N3/04 ,  G06F9/30 ,  G06F9/38 ,  G06T1/20 ,  G06N3/08 ,  G06F16/17

Abstract: One embodiment provides a graphics processor comprising an instruction cache to store an instruction and a compute block configured to perform multiply-accumulate operations in response to execution of the instruction. The compute block includes a scheduler to schedule a plurality of threads for execution of the instruction and multiply-accumulate circuitry configured to execute the instruction via the plurality of threads, wherein the multiply-accumulate circuitry includes a plurality of functional units configured to process, in parallel via the plurality of threads, a corresponding plurality of matrix elements to multiply a first matrix and a second matrix, and to multiply the first matrix and the second matrix includes to multiply data elements in a row of the first matrix by corresponding data elements in a column of the second matrix to generate a plurality of products.

公开(公告)号：US20210373886A1

公开(公告)日：2021-12-02

申请号：US17443376

申请日：2021-07-26

Applicant: Intel Corporation

Inventor： Kevin Nealis ,  Anbang Yao ,  Xiaoming Chen ,  Elmoustapha Ould-Ahmed-Vall ,  Sara S. Baghsorkhi ,  Eriko Nurvitadhi ,  Balaji Vembu ,  Nicolas C. Galoppo Von Borries ,  Rajkishore Barik ,  Tsung-Han Lin ,  Kamal Sinha

IPC: G06F9/30 ,  G06F9/38 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08 ,  G06T1/20

Abstract: One embodiment provides for a compute apparatus comprising a decode unit to decode a single instruction into a decoded instruction that specifies multiple operands including a multi-bit input value and a ternary weight associated with a neural network and an arithmetic logic unit including a multiplier, an adder, and an accumulator register. To execute the decoded instruction, the multiplier is to perform a multiplication operation on the multi-bit input based on the ternary weight to generate an intermediate product and the adder is to add the intermediate product to a value stored in the accumulator register and update the value stored in the accumulator register.

公开(公告)号：US11138686B2

公开(公告)日：2021-10-05

申请号：US16446265

申请日：2019-06-19

Applicant: Intel Corporation

Inventor： Elmoustapha Ould-Ahmed-Vall ,  Sara S. Baghsorkhi ,  Anbang Yao ,  Kevin Nealis ,  Xiaoming Chen ,  Altug Koker ,  Abhishek R. Appu ,  John C. Weast ,  Mike B. Macpherson ,  Dukhwan Kim ,  Linda L. Hurd ,  Ben J. Ashbaugh ,  Barath Lakshmanan ,  Liwei Ma ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland

IPC: G06T1/20 ,  G06F7/483 ,  G06N3/08 ,  G06F9/30 ,  G06N3/04 ,  G06N3/063 ,  G06F9/50 ,  G06F9/38 ,  G06N20/00 ,  G06F3/14 ,  G06T1/60 ,  G06T15/00

Abstract: Embodiments described herein provide a graphics processor that can perform a variety of mixed and multiple precision instructions and operations. One embodiment provides a streaming multiprocessor that can concurrently execute multiple thread groups, wherein the streaming multiprocessor includes a single instruction, multiple thread (SIMT) architecture and the streaming multiprocessor is to execute multiple threads for each of multiple instructions. The streaming multiprocessor can perform concurrent integer and floating-point operations and includes a mixed precision core to perform operations at multiple precisions.

公开(公告)号：US20190304053A1

公开(公告)日：2019-10-03

申请号：US16446265

申请日：2019-06-19

Applicant: Intel Corporation

Inventor： Elmoustapha Ould-Ahmed-Vall ,  Sara S. Baghsorkhi ,  Anbang Yao ,  Kevin Nealis ,  Xiaoming Chen ,  Altug Koker ,  Abhishek R. Appu ,  John C. Weast ,  Mike B. Macpherson ,  Dukhwan Kim ,  Linda L. Hurd ,  Ben J. Ashbaugh ,  Barath Lakshmanan ,  Liwei Ma ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland

IPC: G06T1/20 ,  G06N20/00 ,  G06F7/483

Abstract: Embodiments described herein provide a graphics processor that can perform a variety of mixed and multiple precision instructions and operations. One embodiment provides a streaming multiprocessor that can concurrently execute multiple thread groups, wherein the streaming multiprocessor includes a single instruction, multiple thread (SIMT) architecture and the streaming multiprocessor is to execute multiple threads for each of multiple instructions. The streaming multiprocessor can perform concurrent integer and floating-point operations and includes a mixed precision core to perform operations at multiple precisions.

公开(公告)号：US20190206020A1

公开(公告)日：2019-07-04

申请号：US16197821

申请日：2018-11-21

Applicant: Intel Corporation

Inventor： Elmoustapha Ould-Ahmed-Vall ,  Sara S. Baghsorkhi ,  Anbang Yao ,  Kevin Nealis ,  Xiaoming Chen ,  Altug Koker ,  Abhishek R. Appu ,  John C. Weast ,  Mike B. Macpherson ,  Dukhwan Kim ,  Linda L. Hurd ,  Ben J. Ashbaugh ,  Barath Lakshmanan ,  Liwei Ma ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland

IPC: G06T1/20 ,  G06F7/483 ,  G06N20/00

CPC classification number: G06T1/20 ,  G06F3/14 ,  G06F7/483 ,  G06F9/30014 ,  G06F9/30185 ,  G06F9/3863 ,  G06F9/5044 ,  G06N3/0445 ,  G06N3/0454 ,  G06N3/063 ,  G06N3/084 ,  G06N20/00 ,  G06T1/60 ,  G06T15/005

Abstract: One embodiment provides an accelerator module comprising a memory stack including multiple memory dies; a graphics processing unit (GPU) coupled with the memory stack via one or more memory controllers, the GPU including a plurality of multiprocessors having a single instruction, multiple thread (SIMT) architecture, the multiprocessors to execute at least one single instruction. The at least one single instruction is to cause at least a portion of the GPU to perform a floating point operation on input having differing precisions. The floating point operation is a two-dimensional matrix multiply and accumulate operation.

公开(公告)号：US10186011B2

公开(公告)日：2019-01-22

申请号：US15581182

申请日：2017-04-28

Applicant: Intel Corporation

Inventor： Eriko Nurvitadhi ,  Balaji Vembu ,  Nicolas C. Galoppo Von Borries ,  Rajkishore Barik ,  Tsung-Han Lin ,  Kamal Sinha ,  Nadathur Rajagopalan Satish ,  Jeremy Bottleson ,  Farshad Akhbari ,  Altug Koker ,  Narayan Srinivasa ,  Dukhwan Kim ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Feng Chen ,  Elmoustapha Ould-Ahmed-Vall ,  Kevin Nealis ,  Xiaoming Chen ,  Anbang Yao

IPC: G06T1/20 ,  G06N3/08 ,  G06N3/04

Abstract: One embodiment provides for a compute apparatus to perform machine learning operations, the compute apparatus comprising a decode unit to decode a single instruction into a decoded instruction, the decoded instruction to cause the compute apparatus to perform a complex machine learning compute operation.

公开(公告)号：US20250117874A1

公开(公告)日：2025-04-10

申请号：US18908445

申请日：2024-10-07

Applicant: Intel Corporation

Inventor： Elmoustapha Ould-Ahmed-Vall ,  Sara S. Baghsorkhi ,  Anbang Yao ,  Kevin Nealis ,  Xiaoming Chen ,  Altug Koker ,  Abhishek R. Appu ,  John C. Weast ,  Mike B. Macpherson ,  Dukhwan Kim ,  Linda L. Hurd ,  Ben J. Ashbaugh ,  Barath Lakshmanan ,  Liwei Ma ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland

IPC: G06F17/16 ,  G06F7/544

Abstract: One embodiment provides an apparatus comprising a memory stack including multiple memory dies and a parallel processor including a plurality of multiprocessors. Each multiprocessor has a single instruction, multiple thread (SIMT) architecture, the parallel processor coupled to the memory stack via one or more memory interfaces. At least one multiprocessor comprises a multiply-accumulate circuit to perform multiply-accumulate operations on matrix data in a stage of a neural network implementation to produce a result matrix comprising a plurality of matrix data elements at a first precision, precision tracking logic to evaluate metrics associated with the matrix data elements and indicate if an optimization is to be performed for representing data at a second stage of the neural network implementation, and a numerical transform unit to dynamically perform a numerical transform operation on the matrix data elements based on the indication to produce transformed matrix data elements at a second precision.

公开(公告)号：US12112397B2

公开(公告)日：2024-10-08

申请号：US18334733

申请日：2023-06-14

Applicant: Intel Corporation

Inventor： Eriko Nurvitadhi ,  Balaji Vembu ,  Nicolas C. Galoppo Von Borries ,  Rajkishore Barik ,  Tsung-Han Lin ,  Kamal Sinha ,  Nadathur Rajagopalan Satish ,  Jeremy Bottleson ,  Farshad Akhbari ,  Altug Koker ,  Narayan Srinivasa ,  Dukhwan Kim ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Feng Chen ,  Elmoustapha Ould-Ahmed-Vall ,  Kevin Nealis ,  Xiaoming Chen ,  Anbang Yao

IPC: G06T1/20 ,  G06F9/30 ,  G06F9/38 ,  G06N3/04 ,  G06N3/044 ,  G06N3/045 ,  G06N3/063 ,  G06N3/08 ,  G06N3/084

CPC classification number: G06T1/20 ,  G06F9/3001 ,  G06F9/3017 ,  G06F9/3851 ,  G06F9/3887 ,  G06F9/3895 ,  G06N3/04 ,  G06N3/044 ,  G06N3/045 ,  G06N3/063 ,  G06N3/08 ,  G06N3/084

Abstract: One embodiment provides a parallel processor comprising a hardware scheduler to schedule pipeline commands for compute operations to one or more of multiple types of compute units, a plurality of processing resources including a first sparse compute unit configured for input at a first level of sparsity and hybrid memory circuitry including a memory controller, a memory interface, and a second sparse compute unit configured for input at a second level of sparsity that is greater than the first level of sparsity.