公开(公告)号：US10997771B2

公开(公告)日：2021-05-04

申请号：US16116158

申请日：2018-08-29

Applicant: Intel Corporation

Inventor： Travis Schluessler ,  Zack Waters ,  Michael Apodaca ,  Daniel Johnston ,  Jason Surprise ,  Prasoonkumar Surti ,  Subramaniam Maiyuran ,  Peter Doyle ,  Saurabh Sharma ,  Ankur Shah ,  Murali Ramadoss

IPC: G06T15/00 ,  G06T15/40 ,  G06T15/80

Abstract: Position-based rendering apparatus and method for multi-die/GPU graphics processing. For example, one embodiment of a method comprises: distributing a plurality of graphics draws to a plurality of graphics processors; performing position-only shading using vertex data associated with tiles of a first draw on a first graphics processor, the first graphics processor responsively generating visibility data for each of the tiles; distributing subsets of the visibility data associated with different subsets of the tiles to different graphics processors; limiting geometry work to be performed on each tile by each graphics processor using the visibility data, each graphics processor to responsively generate rendered tiles; and wherein the rendered tiles are combined to generate a complete image frame.

公开(公告)号：US20200074714A1

公开(公告)日：2020-03-05

申请号：US16566989

申请日：2019-09-11

Applicant: Intel Corporation

Inventor： Michael Apodaca ,  Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Murali Ramadoss ,  Abhishek Venkatesh ,  Jonathan Kennedy ,  Slawomir Grajewski

IPC: G06T15/00 ,  G06T3/40

Abstract: A computing system to obtain an output includes a multi-plane rendering module includes a renderer receives a plurality of graphical objects to generate one or more image planes of object data, a resampler upscales lower resolution image planes to a higher resolution used by the output image, and a rasterizer combine pixels from a common location in the plurality of image planes after each image plane is upsampled to the higher resolution. The renderer receives one of the graphical objects having a location value along a z-axis of the scene, determines which of a plurality of image planes the graphical objects is located using the z-axis location for the graphical object, each of the planes possess a corresponding image resolution, and renders the graphical object into the image plane at the image resolution corresponding determined image plane.

公开(公告)号：US10558496B2

公开(公告)日：2020-02-11

申请号：US15865114

申请日：2018-01-08

Applicant: INTEL CORPORATION

Inventor： Michael Apodaca

IPC: G09G5/39 ,  G06F9/50 ,  G06F12/1009

Abstract: Various embodiments are presented herein that may allow an application direct access to graphical processing unit memory. An apparatus and a computer-implemented method may include accessing allocated graphical processing unit memory of a second resource via a link from a first resource. The allocated graphical processing unit memory may be mapped into one or more page tables of a central processing unit. A virtual address of the graphical processing unit memory from the one or more page tables of the central processing unit may be sent to the application.

公开(公告)号：US10522114B2

公开(公告)日：2019-12-31

申请号：US15992642

申请日：2018-05-30

Applicant: Intel Corporation

Inventor： Jeffery S. Boles ,  Hema C. Nalluri ,  Balaji Vembu ,  Michael Apodaca ,  Altug Koker ,  Lalit K. Saptarshi

IPC: G06F12/0846 ,  G06F3/06 ,  G06T1/60 ,  G09G5/36 ,  G06T1/20 ,  G06F12/0895 ,  G06F12/0875

Abstract: In accordance with some embodiments, a command streamer may use a cache of programmable size to cache commands to improve memory bandwidth and reduce latency. The size of the command cache may be programmably set by the command streamer.

公开(公告)号：US20190287290A1

公开(公告)日：2019-09-19

申请号：US16271368

申请日：2019-02-08

Applicant: Intel Corporation

Inventor： Chandrasekaran Sakthivel ,  Michael Apodaca ,  Kai Xiao ,  Altug Koker ,  Jeffery S. Boles ,  Adam T. Lake ,  Nikos Kaburlasos ,  Joydeep Ray ,  John H. Feit ,  Travis T. Schluessler ,  Jacek Kwiatkowski ,  James M. Holland ,  Prasoonkumar Surti ,  Jonathan Kennedy ,  Louis Feng ,  Barnan Das ,  Narayan Biswal ,  Stanley J. Baran ,  Gokcen Cilingir ,  Nilesh V. Shah ,  Archie Sharma ,  Mayuresh M. Varerkar

IPC: G06T15/06 ,  G06F3/01 ,  H04S7/00 ,  G06T19/00 ,  G06T15/00

Abstract: Systems, apparatuses and methods may provide away to render augmented reality and virtual reality (VR/AR) environment information. More particularly, systems, apparatuses and methods may provide a way to selectively suppress and enhance VR/AR renderings of n-dimensional environments. The systems, apparatuses and methods may deepen a user's VR/AR experience by focusing on particular feedback information, while suppressing other feedback information from the environment.

公开(公告)号：US20180300944A1

公开(公告)日：2018-10-18

申请号：US15488641

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Murali Ramadoss ,  Michael Apodaca ,  Abhishek Venkatesh ,  Joydeep Ray ,  Abhishek R. Appu

IPC: G06T15/50 ,  G06T15/80 ,  G06T17/20 ,  G06T7/13 ,  G06T7/136 ,  G06T15/00

CPC classification number: G06T15/503 ,  G06T7/13 ,  G06T7/136 ,  G06T15/005

Abstract: Systems, apparatuses and methods may provide away to render edges of an object defined by multiple tessellation triangles. More particularly, systems, apparatuses and methods may provide a way to perform anti-aliasing at the edges of the object based on a coarse pixel rate, where the coarse pixels may be based on a coarse Z value indicate a resolution or granularity of detail of the coarse pixel. The systems, apparatuses and methods may use a shader dispatch engine to dispatch raster rules to a pixel shader to direct the pixel shader to include, in a tile and/or tessellation triangle, one more finer coarse pixels based on a percent of coverage provided by a finer coarse pixel of a tessellation triangle at or along the edge of the object.

公开(公告)号：US20180300098A1

公开(公告)日：2018-10-18

申请号：US15489096

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Deepak S. Vembar ,  Atsuo Kuwahara ,  Chandrasekaran Sakthivel ,  Radhakrishnan Venkataraman ,  Brent E. Insko ,  Anupreet S. Kalra ,  Hugues Labbe ,  Altug Koker ,  Michael Apodaca ,  Kai Xiao ,  Jeffery S. Boles ,  Adam T. Lake ,  David M. Cimini ,  Balaji Vembu ,  Elmoustapha Ould-Ahmed-Vall ,  Jacek Kwiatkowski ,  Philip R. Laws ,  Ankur N. Shah ,  Abhishek R. Appu ,  Joydeep Ray ,  Wenyin Fu ,  Nikos Kaburlasos ,  Prasoonkumar Surti ,  Bhushan M. Borole

IPC: G06F3/14 ,  H04L29/06

Abstract: An embodiment of a graphics apparatus may include a processor, memory communicatively coupled to the processor, and a collaboration engine communicatively coupled to the processor to identify a shared graphics component between two or more users in an environment, and share the shared graphics components with the two or more users in the environment. Embodiments of the collaboration engine may include one or more of a centralized sharer, a depth sharer, a shared preprocessor, a multi-port graphics subsystem, and a decode sharer. Other embodiments are disclosed and claimed.

公开(公告)号：US20180293703A1

公开(公告)日：2018-10-11

申请号：US15483829

申请日：2017-04-10

Applicant: Intel Corporation

Inventor： Karthik Vaidyanathan ,  Prasoonkumar Surti ,  Michael Apodaca ,  Murali Ramadoss ,  Abhishek Venkatesh ,  Joydeep Ray ,  Abhishek R. Appu

IPC: G06T1/60 ,  G06T9/00

Abstract: An embodiment of a graphics apparatus may include an embedded local memory, and a memory extender communicatively coupled to the embedded local memory to extend the embedded local memory. The memory extender may be configured to compress information and store the compressed information in the embedded local memory. Additionally, or alternatively, the memory extender may be configured to expose the embedded local memory for non-local access. Other embodiments are disclosed and claimed.

公开(公告)号：US20180286106A1

公开(公告)日：2018-10-04

申请号：US15477028

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Michael Apodaca ,  Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Murali Ramadoss ,  Abhishek Venkatesh ,  Jonathan Kennedy ,  Slawomir Grajewski

IPC: G06T15/20 ,  G06T15/00 ,  G06T7/50 ,  G06T7/70 ,  G06T1/20 ,  G06T3/40

Abstract: A computing system to obtain an output includes a multi-plane rendering module includes a renderer receives a plurality of graphical objects to generate one or more image planes of object data, a resampler upscales lower resolution image planes to a higher resolution used by the output image, and a rasterizer combine pixels from a common location in the plurality of image planes after each image plane is upsampled to the higher resolution. The renderer receives one of the graphical objects having a location value along a z-axis of the scene, determines which of a plurality of image planes the graphical objects is located using the z-axis location for the graphical object, each of the planes possess a corresponding image resolution, and renders the graphical object into the image plane at the image resolution corresponding determined image plane.

公开(公告)号：US20180285109A1

公开(公告)日：2018-10-04

申请号：US15477012

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Altug Koker ,  Michael Apodaca ,  Kai Xiao ,  Chandrasekaran Sakthivel ,  Jeffery S. Boles ,  Adam T. Lake ,  Abhishek R. Appu

IPC: G06F9/30 ,  G06T1/60 ,  G06F9/50 ,  G06F12/0802 ,  G06T15/00 ,  G09G5/36 ,  G06T1/20

Abstract: Systems, apparatuses and methods may provide for technology that activates a first context on a graphics processor and detects a context switch condition with respect to the first context. Additionally, a second context may be activated, in response to the context switch condition, on the graphics processor while the first context is active on the graphics processor. In one example, activating the second context includes adding a group identifier to a plurality of threads corresponding to the second context and launching the plurality of threads with the group identifier on the graphics processor.