公开(公告)号：US20190050279A1

公开(公告)日：2019-02-14

申请号：US15818429

申请日：2017-11-20

Applicant: Intel Corporation

Inventor： Michael N. Derr ,  Balaji Vembu ,  Michael Mishaeli ,  Brent Chartrand ,  Bryan R. White ,  Gustavo Espinosa ,  Prashant D. Chaudhari

IPC: G06F11/07

Abstract: Various systems and methods for error handling are described herein. A system for error reporting and handling includes a common error handler that handles errors for a plurality of hardware devices, where the common error handler is operable with other parallel error reporting and handling mechanisms. The common error handler may be used to receive an error message from a hardware device, the error message related to an error; identify a source of the error message; identify a class of the error; identify an error definition of the error; determine whether the error requires a diagnostics operation as part of the error handling; initiate the diagnostics operation when the error requires the diagnostics operation; and clear the error at the hardware device.

公开(公告)号：US20230297159A1

公开(公告)日：2023-09-21

申请号：US18185008

申请日：2023-03-16

Applicant: Intel Corporation

Inventor： Kenneth Daxer ,  Stephen H. Gunther ,  Michael N. Derr ,  Eric Samson

IPC: G06F1/3287 ,  G06F1/329

CPC classification number: G06F1/3287 ,  G06F1/329

Abstract: Described herein, in one embodiment, are techniques to facilitate the partial powerdown of sub-components of an execution unit or other graphics processing resource based on the workload to be executed. In another embodiment, granular dynamic voltage and frequency scaling is enabled in which the voltage and frequency of groups of processing resources within a graphics processor can be separately scaled.

公开(公告)号：US11043158B2

公开(公告)日：2021-06-22

申请号：US15863396

申请日：2018-01-05

Applicant: Intel Corporation

Inventor： Prashant D. Chaudhari ,  Michael N. Derr ,  Paul Diefenbaugh ,  Sameer Kalathil Perazhi ,  Fong-Shek Lam ,  Arthur Jeremy Runyan ,  Jason Tanner

IPC: G09G3/20 ,  G06T1/60 ,  G06F3/14 ,  G06T9/00 ,  H04N19/426

Abstract: Various systems and methods for managing graphics subsystems are described herein. A system for managing graphics subsystems of a compute device includes a display controller operable to: receive an indication that a first display of the compute device has been activated; enable a power management feature in a display controller, the power management feature to reduce power consumption of the display controller and associated components, and the power management feature to reduce graphics memory bandwidth usage; receive an indication that a second display has been activated with the first display; and maintain the power management feature for at least the first display.

公开(公告)号：US20190102861A1

公开(公告)日：2019-04-04

申请号：US15721273

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Prashant D. Chaudhari ,  Michael N. Derr ,  Arthur J. Runyan

IPC: G06T1/60 ,  G09G5/395

CPC classification number: G06T1/60 ,  G06T1/20 ,  G09G5/363 ,  G09G5/395 ,  G09G2320/0257 ,  G09G2330/026 ,  G09G2330/08 ,  G09G2330/12 ,  G09G2354/00 ,  G09G2360/12 ,  G09G2360/127 ,  G09G2360/18 ,  G09G2380/10

Abstract: Various techniques for providing a fault-tolerant graphics display engine are disclosed herein. In an example, a machine identifies a buffer under-run at a data buffer (DBUF) of a display engine. The machine adjusts a latency tolerance of the DBUF in response to identifying the buffer under-run. The machine determines that the buffer under-run at the DBUF persists after adjusting the latency tolerance. The machine determines whether a preset correction limit has been reached. If the preset correction limit has not been reached, the machine further adjusts the latency tolerance of the DBUF. If the preset correction limit has been reached, the machine removes, from a visual output associated with the display engine, one or more non-critical display assets.