公开(公告)号：US11114421B2

公开(公告)日：2021-09-07

申请号：US16546280

申请日：2019-08-20

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Wee Hoe ,  Khang Choong Yong ,  Ping Ping Ooi

IPC: H05K1/00 ,  H05K1/02 ,  H05K1/11 ,  H05K1/18 ,  H05K3/30 ,  H01L23/00 ,  H01L23/36 ,  H01L23/48 ,  H01L23/64 ,  H01L23/495 ,  H01L23/498 ,  H01L25/16 ,  H01L25/18 ,  H01L25/065 ,  H01L23/538 ,  H01L25/00 ,  H05K1/14

Abstract: Methods and apparatus relating to integrating System in Package (SiP) with Input/Output (IO) board for platform miniaturization are described. In an embodiment, a SiP board includes a plurality of logic components. An IO board is coupled to the SiP board via a grid array. The plurality of logic components is provided on both sides of the SiP board and one or more of the plurality of logic components are to positioned in an opening in the IO board. Other embodiments are also disclosed and claimed.

公开(公告)号：US20200084880A1

公开(公告)日：2020-03-12

申请号：US16469105

申请日：2017-11-22

Applicant: Intel Corporation

Inventor： Ping Ping Ooi ,  Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Kool Chi Ooi

IPC: H05K1/02 ,  H01L23/498 ,  H01L21/48 ,  H01L23/538 ,  H01L25/065

Abstract: A multi-conductor interconnect for a microelectronic device incorporates multiple conductors and integrated shielding for the conductors. The multi-conductor interconnect includes first and second groups of conductors interleaved with one another within a dielectric structure. One of the groups of conductors may be coupled to a reference voltage node to provide shielding for the other group of conductors. The multi-conductor interconnect may further include a shield layer extending over some portion, or all, of the conductors of the first and second groups.

公开(公告)号：US10403604B2

公开(公告)日：2019-09-03

申请号：US15766150

申请日：2015-11-05

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Ping Ping Ooi ,  Kooi Chi Ooi ,  Shanggar Periaman

IPC: H01L25/065 ,  H01L23/552 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00 ,  H01L21/56 ,  H01L23/498 ,  H01L23/50

Abstract: Embodiments of the present disclosure are directed toward a stacked package assembly for embedded dies and associated techniques and configurations. In one embodiment, stacked package assembly may comprise a first die package and a second die package stacked one upon the other with plural interconnections between them; and a voltage reference plane embedded in at least one of the first and second die packages in proximity and generally parallel to the other of the first and second die packages.

公开(公告)号：US10317938B2

公开(公告)日：2019-06-11

申请号：US14604531

申请日：2015-01-23

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Khai Ern See ,  Damien Weng Kong Chong ,  Min Suet Lim ,  Ping Ping Ooi ,  Chu Aun Lim ,  Jimmy Huat Since Huang ,  Poh Tat Oh ,  Teong Keat Beh ,  Jackson Chung Peng Kong ,  Fern Nee Tan ,  Jenn Chuan Cheng

IPC: G06F1/16 ,  H05K1/18 ,  G06F1/18 ,  G06F13/38

Abstract: Embodiments are generally directed to an apparatus utilizing computer on package construction. An embodiment of a computer includes a substrate; one or more semiconductor devices, the one or more semiconductor devices being direct chip attached to the substrate, the one or more semiconductor devices including a central processing unit (CPU); and one or more additional components installed on the substrate, wherein the computer excludes I/O components.

公开(公告)号：US20180226357A1

公开(公告)日：2018-08-09

申请号：US15889471

申请日：2018-02-06

Applicant: Intel Corporation

Inventor： Jackson Chung Peng Kong ,  Bok Eng Cheah ,  Ping Ping Ooi ,  Paik Wen Ong ,  Kooi Chi Ooi

IPC: H01L23/552 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/552 ,  H01L21/4857 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/49894 ,  H01L23/50 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/15311 ,  H05K3/4038 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A semiconductor package is disclosed. The semiconductor package includes a multilayer package substrate. The layers of the multi-layer substrate include one or more conductive layers to transmit information within the semiconductor package. The layers also include one or more conductive power supply layers to provide power to the semiconductor package and to one or more connected components. The layers also include one or more layers of dielectric material forming a substrate core dielectric. The layers also include an embedded reference plane within the substrate core dielectric, wherein the embedded reference plane is conductive and reduces electrical interference between the other conductive layers in the multilayer package substrate.

公开(公告)号：US11837458B2

公开(公告)日：2023-12-05

申请号：US17498089

申请日：2021-10-11

Applicant: Intel Corporation

Inventor： Jackson Chung Peng Kong ,  Bok Eng Cheah ,  Ping Ping Ooi ,  Kooi Chi Ooi

IPC: H01L23/66 ,  H01L21/48 ,  H01L23/498 ,  H01L21/768 ,  H01L23/48 ,  H05K3/00 ,  H05K3/42

CPC classification number: H01L23/66 ,  H01L21/481 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49894 ,  H01L21/76898 ,  H01L23/481 ,  H01L2223/6616 ,  H05K3/0094 ,  H05K3/426

Abstract: An electronic circuit including a substrate having a first dielectric characteristic. The substrate can include a first side and a second side. An intermediary material can be disposed within the substrate. For instance, the intermediary material can be located between the first side and the second side. The intermediary material can include a second dielectric characteristic, where the second dielectric characteristic is different than the first dielectric characteristic. A first conductive layer can be disposed on the first side, and a second conductive layer can be disposed on the second side. A conductive path can be electrically coupled between the first conductive layer and the second conductive layer. The conductive path can be in contact with at least a portion of the intermediary material.

公开(公告)号：US11121074B2

公开(公告)日：2021-09-14

申请号：US16819963

申请日：2020-03-16

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Mooi Ling Chang ,  Ping Ping Ooi ,  Jackson Chung Peng Kong ,  Wen Wei Lum

IPC: H01L23/522 ,  H01L49/02 ,  H01L25/16 ,  H01L23/00 ,  H01G4/30 ,  H01L25/065 ,  H01G4/40 ,  H01G4/38 ,  H01L23/538 ,  H01L23/50

Abstract: A stacked-die and stacked-capacitor package vertically arranged capacitors to mirror a semiconductive-device stack. The stacked capacitor can be electrically coupled to one or more semiconductive devices in the stacked architecture.

公开(公告)号：US10980108B2

公开(公告)日：2021-04-13

申请号：US16469105

申请日：2017-11-22

Applicant: Intel Corporation

Inventor： Ping Ping Ooi ,  Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Kooi Chi Ooi

IPC: H05K1/02 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00

Abstract: A multi-conductor interconnect for a microelectronic device incorporates multiple conductors and integrated shielding for the conductors. The multi-conductor interconnect includes first and second groups of conductors interleaved with one another within a dielectric structure. One of the groups of conductors may be coupled to a reference voltage node to provide shielding for the other group of conductors. The multi-conductor interconnect may further include a shield layer extending over some portion, or all, of the conductors of the first and second groups.

公开(公告)号：US20190311978A1

公开(公告)日：2019-10-10

申请号：US16280850

申请日：2019-02-20

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Ping Ping Ooi ,  Shaw Fong Wong ,  Jackson Chung Peng Kong ,  Hungying Lo

IPC: H01L23/498 ,  H05K1/18 ,  H01L23/00 ,  H01L25/16 ,  H01L21/48 ,  H05K3/34

Abstract: A semiconductor package substrate includes a composite and stacked vertical interconnect on a land side of the substrate. The composite and stacked vertical interconnect includes a smaller contact end against the semiconductor package substrate, and a larger contact end for board mounting.

公开(公告)号：US10388636B2

公开(公告)日：2019-08-20

申请号：US15777458

申请日：2015-12-21

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Wee Hoe ,  Khang Choong Yong ,  Ping Ping Ooi

IPC: H05K1/18 ,  H05K3/30 ,  H05K7/00 ,  H01L25/16 ,  H01L23/48 ,  H01L25/065 ,  H01L25/18 ,  H01L23/538 ,  H01L25/00 ,  H05K1/14

Abstract: Methods and apparatus relating to integrating System in Package (SiP) with Input/Output (IO) board for platform miniaturization are described. In an embodiment, a SiP board includes a plurality of logic components. An IO board is coupled to the SiP board via a grid array. The plurality of logic components is provided on both sides of the SiP board and one or more of the plurality of logic components are to positioned in an opening in the IO board. Other embodiments are also disclosed and claimed.