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    INSTRUCTIONS AND LOGIC TO FORK PROCESSES OF SECURE ENCLAVES AND ESTABLISH CHILD ENCLAVES IN A SECURE ENCLAVE PAGE CACHE
    11.
    发明申请
    INSTRUCTIONS AND LOGIC TO FORK PROCESSES OF SECURE ENCLAVES AND ESTABLISH CHILD ENCLAVES IN A SECURE ENCLAVE PAGE CACHE 有权
    指示和逻辑安全保护程序，并在安全的页面缓存中建立儿童安全

    公开(公告)号：US20160246720A1

    公开(公告)日：2016-08-25

    申请号：US14629132

    申请日：2015-02-23

    Applicant: Intel Corporation

    Inventor： Prashant Pandey ,  Mona Vij ,  Somnath Chakrabarti ,  Krystof C. Zmudzinski

    IPC: G06F12/08 ,  G06F12/14 ,  G06F13/24 ,  G06F9/30

    CPC classification number: G06F21/12 ,  G06F12/0811 ,  G06F12/0822 ,  G06F12/0875 ,  G06F12/14 ,  G06F12/1425 ,  G06F13/24 ,  G06F2212/1052 ,  G06F2212/283 ,  G06F2212/452

    Abstract: Instructions and logic fork processes and establish child enclaves in a secure enclave page cache (EPC). Instructions specify addresses for secure storage allocated to enclaves of a parent and a child process to store secure enclave control structure (SECS) data, application data, code, etc. The processor includes an EPC to store enclave data of the parent and child processes. Embodiments of the parent may execute, or a system may execute an instruction to copy parent SECS to secure storage for the child, initialize a unique child ID and link to the parent's SECS/ID. Embodiments of the child may execute, or the system may execute an instruction to copy pages from the parent enclave to the enclave of the child where both have the same key, set an entry for EPC mapping to partial completion, and record a page state in the child enclave, if interrupted. Thus copying can be resumed.

    Abstract translation: 指令和逻辑fork处理并在安全的飞地页面缓存（EPC）中建立子空间。 指令指定分配给父节点和子进程的子进程的安全存储地址，以存储安全区域控制结构（SECS）数据，应用程序数据，代码等。处理器包括用于存储父进程和子进程的飞地数据的EPC。 父级的实施例可以执行，或者系统可以执行复制父SECS以保护儿童的存储的指令，初始化唯一的子ID并链接到父级的SECS / ID。 子系统的实施例可以执行，或者系统可以执行将父页面的页面复制到具有相同密钥的小孩的飞地的指令，将用于EPC映射的条目设置为部分完成，并将页面状态记录在 孩子飞散，如果中断。 因此可以恢复复印。

    Protected container key management processors, methods, systems, and instructions
    14.
    发明授权
    Protected container key management processors, methods, systems, and instructions 有权

    公开(公告)号：US10263988B2

    公开(公告)日：2019-04-16

    申请号：US15201447

    申请日：2016-07-02

    Applicant: Intel Corporation

    Inventor： Mona Vij ,  Somnath Chakrabarti ,  Carlos V. Rozas ,  Asit K. Mallick

    IPC: H04L29/06 ,  G06F21/10 ,  G06F21/62

    Abstract: A processor of an aspect includes a decode unit to decode an instruction. The instruction to indicate a first structure in a protected container memory and to indicate a second structure in the protected container memory. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the instruction, is to determine whether a status indicator is configured to allow at least one key to be exchanged between the first and second structures, and is to exchange the at least one key between the first and second structures when the status indicator is configured to allow the at least one key to be exchanged between the first and second structures.

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