公开(公告)号：US11538806B2

公开(公告)日：2022-12-27

申请号：US16143951

申请日：2018-09-27

Applicant: Intel Corporation

Inventor： Roza Kotlyar ,  Rishabh Mehandru ,  Stephen Cea ,  Biswajeet Guha ,  Dax Crum ,  Tahir Ghani

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/08 ,  H01L29/49

Abstract: Gate-all-around integrated circuit structures having high mobility, and methods of fabricating gate-all-around integrated circuit structures having high mobility, are described. For example, an integrated circuit structure includes a silicon nanowire or nanoribbon. An N-type gate stack is around the silicon nanowire or nanoribbon, the N-type gate stack including a compressively stressing gate electrode. A first N-type epitaxial source or drain structure is at a first end of the silicon nanowire or nanoribbon. A second N-type epitaxial source or drain structure is at a second end of the silicon nanowire or nanoribbon. The silicon nanowire or nanoribbon has a plane between the first N-type epitaxial source or drain structure and the second N-type epitaxial source or drain structure.

公开(公告)号：US10892326B2

公开(公告)日：2021-01-12

申请号：US16475031

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Aaron Lilak ,  Patrick Keys ,  Sean Ma ,  Stephen Cea ,  Rishabh Mehandru

IPC: H01L21/306 ,  H01L21/3105 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66

Abstract: An apparatus is provided which comprises: a plurality of nanowire transistors stacked vertically, wherein each nanowire transistor of the plurality of nanowire transistors comprises a corresponding nanowire of a plurality of nanowires; and a gate stack, wherein the gate stack fully encircles at least a section of each nanowire of the plurality of nanowires.

公开(公告)号：US11923412B2

公开(公告)日：2024-03-05

申请号：US18106374

申请日：2023-02-06

Applicant: Intel Corporation

Inventor： Rishabh Mehandru ,  Stephen Cea ,  Anupama Bowonder ,  Juhyung Nam ,  Willy Rachmady

IPC: H01L23/00 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66818 ,  H01L29/7848 ,  H01L29/7854

Abstract: Embodiments disclosed herein include transistor devices and methods of forming such transistor devices. In an embodiment a transistor comprises a substrate, and a fin that extends up from the substrate. In an embodiment, the fin comprises a source region, a drain region, and a channel region between the source region and the drain region. In an embodiment, the transistor further comprises and a cavity in the fin, where the cavity is below the channel region. In an embodiment, the transistor further comprises a gate stack over the fin.

公开(公告)号：US11843052B2

公开(公告)日：2023-12-12

申请号：US17589831

申请日：2022-01-31

Applicant: Intel Corporation

Inventor： Rishabh Mehandru ,  Tahir Ghani ,  Stephen Cea

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/105 ,  H01L29/41791 ,  H01L29/66795 ,  H01L2029/7858

Abstract: A semiconductor device includes a semiconductor body that includes a surface and a first region and a second region formed in the semiconductor body, where a channel region is located between the first region and the second region, and where the second region includes a sub-region that includes a blanket dopant; a first conductive contact on the surface of the semiconductor body above the first region; a semiconductor-on-insulator (SOI) at a bottom of the first region; and a pocket channel dopant (PCD) formed in the channel, where a first portion of the PCD is adjacent to a first portion of the SOI; and a second conductive contact on a bottom portion of the sub-region, where a first portion of the second conductive contact is adjacent to a second portion of the SOI, and a second portion of the second conductive contact is adjacent to a second portion of the PCD.

公开(公告)号：US20230114214A1

公开(公告)日：2023-04-13

申请号：US17485158

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Stephen Cea ,  Biswajeet Guha ,  Leonard Guler ,  Tahir Ghani ,  Sean Ma

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/66

Abstract: Single-sided nanosheet transistor structures comprising an upper channel material over a lower channel material. A first dielectric material is formed adjacent to a first sidewall of the upper and lower channel materials. A second dielectric material is formed adjacent to a second sidewall of the upper and lower channel materials. The first sidewall of the upper and lower channel materials is exposed by etching at least a portion of the first dielectric material. A sidewall portion of the second dielectric material may be exposed by removing sacrificial material from between the upper and lower channel materials. A single-sided gate stack may then be formed in direct contact with the first sidewall of the upper and lower channel materials, and in contact with the sidewall portion of the second dielectric material.

公开(公告)号：US20230097948A1

公开(公告)日：2023-03-30

申请号：US17485340

申请日：2021-09-25

Applicant: Intel Corporation

Inventor： Rishabh Mehandru ,  Stephen Cea ,  Patrick Keys ,  Aaron Lilak ,  Cory Weber

IPC: H01L27/088 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/02 ,  H01L29/66

Abstract: Integrated circuitry comprising transistor structures having a channel portion over a base portion of fin. The base portion of the fin is an insulative amorphous oxide, or a counter-doped crystalline material. Transistor structures, such as channel portions of a fin and source and drain materials may be first formed with epitaxial processes seeded by a front side of a crystalline substrate. Following front side processing, a backside of the transistor structures may be exposed and the base portion of the fin modified from the crystalline substrate composition into the amorphous oxide or counter-doped crystalline material using backside processes and low temperatures that avoid degradation to the channel material while reducing transistor off-state leakage.

公开(公告)号：US11527612B2

公开(公告)日：2022-12-13

申请号：US16146778

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Glenn Glass ,  Anand Murthy ,  Biswajeet Guha ,  Dax M. Crum ,  Sean Ma ,  Tahir Ghani ,  Susmita Ghose ,  Stephen Cea ,  Rishabh Mehandru

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/285 ,  H01L21/306 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78 ,  H01L21/683

Abstract: Gate-all-around integrated circuit structures having vertically discrete source or drain structures, and methods of fabricating gate-all-around integrated circuit structures having vertically discrete source or drain structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, the first epitaxial source or drain structure including vertically discrete portions aligned with the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, the second epitaxial source or drain structure including vertically discrete portions aligned with the vertical arrangement of horizontal nanowires.

公开(公告)号：US11495683B2

公开(公告)日：2022-11-08

申请号：US16795473

申请日：2020-02-19

Applicant: Intel Corporation

Inventor： Aaron Lilak ,  Patrick Keys ,  Sayed Hasan ,  Stephen Cea ,  Anupama Bowonder

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/737 ,  H01L21/02

Abstract: Multiple strain states in epitaxial transistor channel material may be achieved through the incorporation of stress-relief defects within a seed material. Selective application of strain may improve channel mobility of one carrier type without hindering channel mobility of the other carrier type. A transistor structure may have a heteroepitaxial fin including a first layer of crystalline material directly on a second layer of crystalline material. Within the second layer, a number of defected regions of a threshold minimum dimension are present, which induces the first layer of crystalline material to relax into a lower-strain state. The defected regions may be introduced selectively, for example a through a masked impurity implantation, so that the defected regions may be absent in some transistor structures where a higher-strain state in the first layer of crystalline material is desired.

公开(公告)号：US20210257492A1

公开(公告)日：2021-08-19

申请号：US16795473

申请日：2020-02-19

Applicant: Intel Corporation

Inventor： Aaron Lilak ,  Patrick Keys ,  Sayed Hasan ,  Stephen Cea ,  Anupama Bowonder

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/10 ,  H01L29/08 ,  H01L21/02

Abstract: Multiple strain states in epitaxial transistor channel material may be achieved through the incorporation of stress-relief defects within a seed material. Selective application of strain may improve channel mobility of one carrier type without hindering channel mobility of the other carrier type. A transistor structure may have a heteroepitaxial fin including a first layer of crystalline material directly on a second layer of crystalline material. Within the second layer, a number of defected regions of a threshold minimum dimension are present, which induces the first layer of crystalline material to relax into a lower-strain state. The defected regions may be introduced selectively, for example a through a masked impurity implantation, so that the defected regions may be absent in some transistor structures where a higher-strain state in the first layer of crystalline material is desired.

公开(公告)号：US11984449B2

公开(公告)日：2024-05-14

申请号：US17968558

申请日：2022-10-18

Applicant: Intel Corporation

Inventor： Cory Bomberger ,  Anand Murthy ,  Stephen Cea ,  Biswajeet Guha ,  Anupama Bowonder ,  Tahir Ghani

IPC: H01L27/088 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/267 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/267

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having channel structures with sub-fin dopant diffusion blocking layers are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. The lower fin portion includes a dopant diffusion blocking layer on a first semiconductor layer doped to a first conductivity type. The upper fin portion includes a portion of a second semiconductor layer, the second semiconductor layer on the dopant diffusion blocking layer. An isolation structure is along sidewalls of the lower fin portion. A gate stack is over a top of and along sidewalls of the upper fin portion, the gate stack having a first side opposite a second side. A first source or drain structure at the first side of the gate stack.