公开(公告)号：US20180308280A1

公开(公告)日：2018-10-25

申请号：US15493214

申请日：2017-04-21

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Abhishek R. Appu ,  Subhajit Dasgupta ,  Srivallaba Mysore ,  Michael J. Norris ,  Vasanth Ranganathan ,  Joydeep Ray

IPC: G06T15/80 ,  G06T1/20 ,  G06T1/60 ,  G06T15/00

Abstract: One embodiment provides for a graphics processing unit comprising a processing cluster to perform coarse pixel shading and output shaded coarse pixels for processing by a pixel processing pipeline and a render cache to store coarse pixel data for input to or output from pixel processing pipeline.

公开(公告)号：US20180189926A1

公开(公告)日：2018-07-05

申请号：US15394084

申请日：2016-12-29

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Prasoonkumar Surti ,  Subhajit Dasgupta

IPC: G06T1/60 ,  G06T1/20

CPC classification number: G06T1/60 ,  G06T1/20 ,  G06T2200/28

Abstract: Methods and apparatus relating to Multi-Sample Anti-Aliasing (MSAA) memory bandwidth reduction for sparse sample per pixel utilization are described. In an embodiment, Multi-Sample Anti-Aliasing (MSAA) logic generates render subspan plane information based on data stored in a cacheline. One or more read operations to memory are suppressed based on a determination that the cacheline is in a clear state. Other embodiments are also disclosed and claimed.

公开(公告)号：US12190441B2

公开(公告)日：2025-01-07

申请号：US18436522

申请日：2024-02-08

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Abhishek R. Appu ,  Subhajit Dasgupta ,  Srivallaba Mysore ,  Michael J. Norris ,  Vasanth Ranganathan ,  Joydeep Ray

IPC: G06T15/80 ,  G06T1/20 ,  G06T1/60 ,  G06T15/00

Abstract: One embodiment provides for a graphics processing unit comprising a processing cluster to perform multi-rate shading via coarse pixel shading and output shaded coarse pixels for processing by a post-shader pixel processing pipeline.

公开(公告)号：US20230094067A1

公开(公告)日：2023-03-30

申请号：US17485244

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Daniel Johnston ,  Yoav Harel ,  Subhajit Dasgupta

IPC: G06T15/04 ,  G06T1/20 ,  G06T1/60 ,  G06T15/00

Abstract: Methods, systems and apparatuses may provide for hardware sampler technology that determines mip region dimensions of a feedback map based on a description of the feedback map, identifies accessed texels in a texture based on a view of a resource that is paired with the feedback map, and records the accessed texels in the feedback map based on the mip region dimensions.

公开(公告)号：US11494968B2

公开(公告)日：2022-11-08

申请号：US17322677

申请日：2021-05-17

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Prasoonkumar Surti ,  Srivallaba Mysore ,  Subhajit Dasgupta ,  Hiroshi Akiba ,  Eric J. Hoekstra ,  Linda L. Hurd ,  Travis T. Schluessler ,  Daren J. Schmidt

IPC: G06T15/00 ,  G06T15/50 ,  G06T1/20 ,  G06F1/3287 ,  G06F9/54

Abstract: Briefly, in accordance with one or more embodiments, a processor receives an incoming data stream that includes alpha channel data, and a memory stores an application programming interface (API). The API is to route the alpha channel data to a fixed point blending unit to perform one or more blending operations using fixed point representation of the alpha channel data. The API is further to route the incoming data stream to a floating point blending unit to perform operations involving floating point representation of the incoming data.