公开(公告)号：US20250142948A1

公开(公告)日：2025-05-01

申请号：US18498318

申请日：2023-10-31

Applicant: Intel Corporation

Inventor： Robin Chao ,  Chiao-Ti Huang ,  Guowei Xu ,  Yang Zhang ,  Ting-Hsiang Hung ,  Tao Chu ,  Feng Zhang ,  Chia-Ching Lin ,  Anand S. Murthy ,  Conor P. Puls ,  Kan Zhang

IPC: H01L27/088 ,  H01L23/498 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

Abstract: An IC device with one or more transistors may also include one or more vias and jumpers for delivering power to the transistors. For instance, a via may be coupled to a power plane. A jumper may be connected to the via and an electrode of a transistor. With the via and jumper, an electrical connection is built between the power plane and the electrode. The via may be self-aligned. The IC device may include a dielectric structure at a first side of the via. A portion of the jumper may be at a second side of the via. The second side opposes the first side. The dielectric structure and the portion of the jumper may be over another dielectric structure that has a different dielectric material from the dielectric structure. The via may be insulated from another electrode of the transistor, which may be coupled to a ground plane.

公开(公告)号：US20250107212A1

公开(公告)日：2025-03-27

申请号：US18471705

申请日：2023-09-21

Applicant: Intel Corporation

Inventor： Yang Zhang ,  Guowei Xu ,  Tao Chu ,  Robin Chao ,  Chiao-Ti Huang ,  Feng Zhang ,  Ting-Hsiang Hung ,  Chia-Ching Lin ,  Anand Murthy

IPC: H01L29/49 ,  H01L21/28 ,  H01L21/78 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: Techniques are provided to form an integrated circuit having an airgap spacer between at least a transistor gate structure and an adjacent source or drain contact. In one such example, a FET (field effect transistor) includes a gate structure that extends around a fin or any number of nanowires (or nanoribbons or nanosheets, as the case may be) of semiconductor material. The semiconductor material may extend in a first direction between source and drain regions while the gate structure extends over the semiconductor material in a second direction. Airgaps are provided in the regions between the gate structures and the adjacent source/drain contacts. The airgaps have a low dielectric constant (e.g., around 1.0) to reduce the parasitic capacitance between the conductive structures.

公开(公告)号：US20240105718A1

公开(公告)日：2024-03-28

申请号：US17934251

申请日：2022-09-22

Applicant: Intel Corporation

Inventor： Tao Chu ,  Guowei Xu ,  Minwoo Jang ,  Yanbin Luo ,  Feng Zhang ,  Ting-Hsiang Hung ,  Chia-Ching Lin

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/08 ,  H01L29/778 ,  H01L29/786

CPC classification number: H01L27/0886 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/778 ,  H01L29/78696

Abstract: Methods for fabricating an integrated circuit (IC) device with a protection liner between doped semiconductor regions are provided. An example IC device includes a channel material having a first face and a second face opposite the first face, a first doped region and a second doped region in the channel material, extending from the second face towards the first face by a first distance; and an insulator structure in a portion of the channel material between the first and second doped regions, the insulator structure extending from the second face towards the first face by a second distance greater than the first distance. The insulator structure includes a first portion between the second face and the first distance and a second portion between first distance and the second distance. The insulator structure includes a liner material on sidewalls of the first portion but absent on sidewalls of the second portion.