公开(公告)号：US11710269B2

公开(公告)日：2023-07-25

申请号：US17876358

申请日：2022-07-28

Applicant: Intel Corporation

Inventor： Travis Schluessler ,  Zack Waters ,  Michael Apodaca ,  Daniel Johnston ,  Jason Surprise ,  Prasoonkumar Surti ,  Subramaniam Maiyuran ,  Peter Doyle ,  Saurabh Sharma ,  Ankur Shah ,  Murali Ramadoss

IPC: G06T15/00 ,  G06T15/40 ,  G06T15/80

CPC classification number: G06T15/005 ,  G06T15/40 ,  G06T15/80 ,  G06T2210/52

Abstract: Position-based rendering apparatus and method for multi-die/GPU graphics processing. For example, one embodiment of a method comprises: distributing a plurality of graphics draws to a plurality of graphics processors; performing position-only shading using vertex data associated with tiles of a first draw on a first graphics processor, the first graphics processor responsively generating visibility data for each of the tiles; distributing subsets of the visibility data associated with different subsets of the tiles to different graphics processors; limiting geometry work to be performed on each tile by each graphics processor using the visibility data, each graphics processor to responsively generate rendered tiles; and wherein the rendered tiles are combined to generate a complete image frame.

公开(公告)号：US20230140640A1

公开(公告)日：2023-05-04

申请号：US17518328

申请日：2021-11-03

Applicant: Intel Corporation

Inventor： Stav Gurtovoy ,  Abhishek Venkatesh ,  Michael Apodaca ,  Travis Schluessler ,  John Feit

IPC: G06T15/00 ,  G06T1/20 ,  G06T1/60 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538

Abstract: Methods, systems and apparatuses may provide for technology that marks a graphics resource as a flush candidate during a current frame, conducts an early flush of a command buffer from the graphics resource if a write event is detected with respect to the graphics resource during a subsequent frame, and bypasses the early flush if the write event is not detected with respect to the graphics resource during the subsequent frame. In one example, the graphics resource is marked as the flush candidate in response to a read back operation of the host processor with respect to the graphics resource, wherein the read back operation retrieves a query result and/or maps a staging resource.

公开(公告)号：US11315213B2

公开(公告)日：2022-04-26

申请号：US17061296

申请日：2020-10-01

Applicant: Intel Corporation

Inventor： Michael Doyle ,  Travis Schluessler ,  Gabor Liktor ,  Atsuo Kuwahara ,  Jefferson Amstutz

IPC: G06T15/10 ,  G06T1/20 ,  G06F16/901 ,  G06F9/38 ,  G06F9/50 ,  G06T15/00 ,  G06T15/06

Abstract: An apparatus comprising a sorting unit to sort primitives of a graphics image, the primitives to be grouped, each group to form a first level node of a hierarchical acceleration structure; a parallel reconfigurable clustering array to construct the hierarchical acceleration structure, the parallel reconfigurable clustering array comprising a plurality of processing clusters, each cluster comprising: parallel efficiency analysis circuitry to evaluate different groupings of the first level nodes for a next level of the hierarchical acceleration structure to determine efficiency values for the different groupings; and node merge circuitry to merge the first level nodes based on the efficiency values to form second level nodes.

公开(公告)号：US11257182B2

公开(公告)日：2022-02-22

申请号：US16943984

申请日：2020-07-30

Applicant: Intel Corporation

Inventor： John Gierach ,  Abhishek Venkatesh ,  Travis Schluessler ,  Devan Burke ,  Tomer Bar-On ,  Michael Apodaca

IPC: G06T1/20 ,  G06T17/10

Abstract: Embodiments are generally directed to GPU mixed primitive topology type processing. An embodiment of an apparatus includes one or more processor cores; and a memory to store data for graphics processing, wherein the one or more processing cores are to generate in the memory a vertex buffer to store vertex data for a mesh to be rendered and an index buffer to index the vertex data stored in the vertex buffer, the index buffer being structured to include index data for multiple primitive topology types. The one or more processor cores are to process the index data for the plurality of primitive topology types from the index buffer and fetch vertex data from the vertex buffer; and are to set up each primitive topology type of the plurality of primitive topology types for processing in a single draw operation.

公开(公告)号：US10997771B2

公开(公告)日：2021-05-04

申请号：US16116158

申请日：2018-08-29

Applicant: Intel Corporation

Inventor： Travis Schluessler ,  Zack Waters ,  Michael Apodaca ,  Daniel Johnston ,  Jason Surprise ,  Prasoonkumar Surti ,  Subramaniam Maiyuran ,  Peter Doyle ,  Saurabh Sharma ,  Ankur Shah ,  Murali Ramadoss

IPC: G06T15/00 ,  G06T15/40 ,  G06T15/80

Abstract: Position-based rendering apparatus and method for multi-die/GPU graphics processing. For example, one embodiment of a method comprises: distributing a plurality of graphics draws to a plurality of graphics processors; performing position-only shading using vertex data associated with tiles of a first draw on a first graphics processor, the first graphics processor responsively generating visibility data for each of the tiles; distributing subsets of the visibility data associated with different subsets of the tiles to different graphics processors; limiting geometry work to be performed on each tile by each graphics processor using the visibility data, each graphics processor to responsively generate rendered tiles; and wherein the rendered tiles are combined to generate a complete image frame.

公开(公告)号：US20200211511A1

公开(公告)日：2020-07-02

申请号：US16723337

申请日：2019-12-20

Applicant: Intel Corporation

Inventor： Travis Schluessler ,  Abhishek Venkatesh ,  John Gierach ,  Tomer Bar-On ,  Devan Burke

IPC: G09G5/36 ,  G09G5/391 ,  G06T15/40 ,  G06T15/20 ,  G06T7/70 ,  G06T15/00 ,  G09G3/00 ,  G06T1/20 ,  G09G5/00

Abstract: Systems, methods and apparatuses may provide for technology to reduce rendering overhead associated with light field displays. The technology may conduct data formatting, re-projection, foveation, tile binning and/or image warping operations with respect to a plurality of display planes in a light field display.

公开(公告)号：US10540260B2

公开(公告)日：2020-01-21

申请号：US15903393

申请日：2018-02-23

Applicant: Intel Corporation

Inventor： Travis Schluessler ,  Abhishek Venkatesh ,  Elmoustapha Ould-Ahmed-Vall ,  John Gierach ,  Tomer Bar On ,  Devan Burke

IPC: G06F9/44 ,  G06F11/36 ,  G06F9/38 ,  G06T1/20

Abstract: In one example, an apparatus comprises processing circuitry to analyze a program at compile time to determine a set of latency parameters associated with instruction sets implemented to execute the program and select a latency management technique based at least in part on the set of latency parameters associated with instruction sets implemented to execute the program. Other examples may be described and claimed.

公开(公告)号：US10522113B2

公开(公告)日：2019-12-31

申请号：US15858486

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Travis Schluessler ,  Abhishek Venkatesh ,  John Gierach ,  Tomer Bar-On ,  Devan Burke

IPC: G06T15/40 ,  G09G5/36 ,  G09G5/391 ,  G06T15/20 ,  G06T7/70 ,  G06T15/00 ,  G09G3/00 ,  G06T1/20 ,  G09G5/00 ,  G06T3/00 ,  G09G5/397 ,  G06T1/60 ,  G06F3/14 ,  G09G5/377

Abstract: Systems, methods and apparatuses may provide for technology to reduce rendering overhead associated with light field displays. The technology may conduct data formatting, re-projection, foveation, tile binning and/or image warping operations with respect to a plurality of display planes in a light field display.

公开(公告)号：US10430189B2

公开(公告)日：2019-10-01

申请号：US15709213

申请日：2017-09-19

Applicant: Intel Corporation

Inventor： Karthik Vaidyanathan ,  Tomasz Janczak ,  Travis Schluessler ,  Subramaniam Maiyuran

IPC: G06F9/30 ,  G06F9/48 ,  G06T15/00 ,  G06F9/50

Abstract: An apparatus to facilitate register allocation is disclosed. The apparatus includes an execution unit (EU) to execute processing threads. The EU includes a plurality of registers and register allocation logic to map the plurality of registers into logical register banks and allocate the processing threads to one or more of the logical register banks.

公开(公告)号：US11960405B2

公开(公告)日：2024-04-16

申请号：US18148749

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Zack S. Waters ,  Travis Schluessler ,  Michael Apodaca ,  Ankur Shah

IPC: G06F12/0882 ,  G06F9/4401 ,  G06F9/50 ,  G06F9/54 ,  G06F11/30 ,  G06F12/06 ,  G06F12/0837 ,  G06F12/1045

CPC classification number: G06F12/0882 ,  G06F9/4411 ,  G06F9/5016 ,  G06F9/544 ,  G06F11/3006 ,  G06F11/3037 ,  G06F12/0607 ,  G06F12/0837 ,  G06F12/1054 ,  G06F12/1063

Abstract: Graphics processors for implementing multi-tile memory management are disclosed. In one embodiment, a graphics processor includes a first graphics device having a local memory, a second graphics device having a local memory, and a graphics driver to provide a single virtual allocation with a common virtual address range to mirror a resource to each local memory of the first and second graphics devices.