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    System, apparatus and method for fine-grain address space selection in a processor
    12.
    发明授权
    System, apparatus and method for fine-grain address space selection in a processor 有权

    公开(公告)号：US11461099B2

    公开(公告)日：2022-10-04

    申请号：US16911441

    申请日：2020-06-25

    Applicant: Intel Corporation

    Inventor： Utkarsh Y. Kakaiya ,  Rajesh Sankaran ,  Gilbert Neiger ,  Philip Lantz ,  Sanjay K. Kumar

    IPC: G06F9/34 ,  G06F9/30 ,  G06F12/109

    Abstract: In one embodiment, a processor comprises: a first configuration register to store a pointer to a process address space identifier (PASID) table; and an execution circuit coupled to the first configuration register. The execution circuit, in response to a first instruction, is to obtain command data from a first location identified in a source operand of the first instruction, obtain a PASID table handle from the command data, access a first entry of the PASID table using the pointer from the first configuration register and the PASID table handle to obtain a PASID value, insert the PASID value into the command data, and send the command data to a device coupled to the processor. Other embodiments are described and claimed.

    Device, method, and system to identify a page request to be processed after a reset event
    13.
    发明授权
    Device, method, and system to identify a page request to be processed after a reset event 有权

    公开(公告)号：US12164444B2

    公开(公告)日：2024-12-10

    申请号：US17357829

    申请日：2021-06-24

    Applicant: Intel Corporation

    Inventor： Ashok Raj ,  Rajesh Sankaran ,  Rupin Vakharwala ,  Utkarsh Y. Kakaiya

    IPC: G06F13/16 ,  G06F13/42 ,  G06F9/455

    Abstract: Techniques and mechanisms for an input-output memory management module (IOMMU) to indicate to software whether a page request by an endpoint device is to be serviced. In an embodiment, the IOMMU receives from the endpoint device a response to an invalidation wait message. Based on the response, the IOMMU provides first information which indicates to software that page requests have been flushed from the endpoint device. Page request message from the endpoint device are compatible with an interface standard which also comprises a stop marker message type. The first information is provided independent of the endpoint device providing any message which is of the stop marker message type. In another embodiment, the first information includes a drain marker generated by the IOMMU, or a snapshot of an address corresponding to an end of a page request queue.

    DEVICE, METHOD, AND SYSTEM TO IDENTIFY A PAGE REQUEST TO BE PROCESSED AFTER A RESET EVENT
    17.
    发明申请
    DEVICE, METHOD, AND SYSTEM TO IDENTIFY A PAGE REQUEST TO BE PROCESSED AFTER A RESET EVENT 有权

    公开(公告)号：US20220414029A1

    公开(公告)日：2022-12-29

    申请号：US17357829

    申请日：2021-06-24

    Applicant: Intel Corporation

    Inventor： Ashok Raj ,  Rajesh Sankaran ,  Rupin Vakharwala ,  Utkarsh Y. Kakaiya

    IPC: G06F13/16 ,  G06F13/42

    Abstract: Techniques and mechanisms for an input-output memory management module (IOMMU) to indicate to software whether a page request by an endpoint device is to be serviced. In an embodiment, the IOMMU receives from the endpoint device a response to an invalidation wait message. Based on the response, the IOMMU provides first information which indicates to software that page requests have been flushed from the endpoint device. Page request message from the endpoint device are compatible with an interface standard which also comprises a stop marker message type. The first information is provided independent of the endpoint device providing any message which is of the stop marker message type. In another embodiment, the first information includes a drain marker generated by the IOMMU, or a snapshot of an address corresponding to an end of a page request queue.

    TECHNIQUES TO ENABLE QUALITY OF SERVICE CONTROL FOR AN ACCELERATOR DEVICE
    18.
    发明申请
    TECHNIQUES TO ENABLE QUALITY OF SERVICE CONTROL FOR AN ACCELERATOR DEVICE 有权

    公开(公告)号：US20220413909A1

    公开(公告)日：2022-12-29

    申请号：US17359409

    申请日：2021-06-25

    Applicant: Intel Corporation

    Inventor： Utkarsh Y. Kakaiya ,  Rajesh M. Sankaran

    IPC: G06F9/48

    Abstract: Examples include techniques to enable quality of service (QoS) control for an accelerator device. Circuitry at an accelerator device implements QoS control responsive to receipt of a submission descriptor for a work request to execute a workload for an application hosted by a compute device coupled with the accelerator device. An example QoS control includes accepting the submission descriptor to a work queue at the accelerator device based on a work size of submission descriptor submissions of the application to the work queue over a unit of time not exceeding a submission rate threshold. The work queue is associated with an operational unit at the accelerator device to execute the workload based on information included in the submission descriptor. The work queue to be shared with at least one other application hosted by the compute device.

    DEVICE MEMORY PROTECTION FOR SUPPORTING TRUST DOMAINS
    19.
    发明申请
    DEVICE MEMORY PROTECTION FOR SUPPORTING TRUST DOMAINS 有权

    公开(公告)号：US20220222185A1

    公开(公告)日：2022-07-14

    申请号：US17712109

    申请日：2022-04-02

    Applicant: Intel Corporation

    Inventor： Vidhya Krishnan ,  Siddhartha Chhabra ,  David Puffer ,  Ankur Shah ,  Daniel Nemiroff ,  Utkarsh Y. Kakaiya

    IPC: G06F12/14 ,  G06F12/02 ,  G06F11/10

    Abstract: Device memory protection for supporting trust domains is described. An example of a computer-readable storage medium includes instructions for allocating device memory for one or more trust domains (TDs) in a system including one or more processors and a graphics processing unit (GPU); allocating a trusted key ID for a TD of the one or more TDs; creating LMTT (Local Memory Translation Table) mapping for address translation tables, the address translation tables being stored in a device memory of the GPU; transitioning the TD to a secure state; and receiving and processing a memory access request associated with the TD, processing the memory access request including accessing a secure version of the address translation tables.

    OPTIMIZATIONS OF BUFFER INVALIDATIONS TO REDUCE MEMORY MANAGEMENT PERFORMANCE OVERHEAD
    20.
    发明申请
    OPTIMIZATIONS OF BUFFER INVALIDATIONS TO REDUCE MEMORY MANAGEMENT PERFORMANCE OVERHEAD 有权

    公开(公告)号：US20220164303A1

    公开(公告)日：2022-05-26

    申请号：US17535289

    申请日：2021-11-24

    Applicant: Intel Corporation

    Inventor： Vinay Raghav ,  Yesha Shah ,  Paras Goyal ,  Utkarsh Y. Kakaiya

    IPC: G06F13/28 ,  G06F12/0891

    Abstract: Methods, apparatus, systems, and articles of manufacture to manage memory in a computing apparatus are disclosed. Methods, apparatus, systems, and articles of manufacture to optimize or improve buffer invalidation to reduce memory management performance overhead are disclosed. An example apparatus includes an input-output memory management unit (IOMMU) circuitry to control access to memory circuitry, the IOMMU circuitry to increment a counter from a first value to a second value when a memory access to a location in the memory circuitry is allocated and to decrement the counter from the second value to the first value when the memory access to the location in the memory circuitry is deallocated; and an operating system (OS) memory manager to enable reallocation of the location in the memory circuitry when the counter is at the first value.

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