公开(公告)号：US09972573B2

公开(公告)日：2018-05-15

申请号：US15393048

申请日：2016-12-28

Applicant: Invensas Corporation

Inventor： Min Tao ,  Hoki Kim ,  Ashok S. Prabhu ,  Zhuowen Sun ,  Wael Zohni ,  Belgacem Haba

IPC: H01L23/538 ,  H01L23/31 ,  H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/52 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/5283 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/09 ,  H01L24/46 ,  H01L24/49 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/071 ,  H01L25/105 ,  H01L25/112 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/02331 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/15151 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/19107

Abstract: Wafer-level packaged components are disclosed. In a wafer-level-packaged, an integrated circuit die has first contacts in an inner third region of a surface of the integrated circuit die. A redistribution layer has second contacts in an inner third region of a first surface of the redistribution layer and third contacts in an outer third region of a second surface of the redistribution layer opposite the first surface thereof. The second contacts of the redistribution layer are coupled for electrical conductivity to the first contacts of the integrated circuit die with the surface of the integrated circuit die face-to-face with the first surface of the redistribution layer. The third contacts are offset from the second contacts for being positioned in a fan-out region for association at least with the outer third region of the second surface of the redistribution layer, the third contacts being surface mount contacts.

公开(公告)号：US20180040587A1

公开(公告)日：2018-02-08

申请号：US15669269

申请日：2017-08-04

Applicant: Invensas Corporation

Inventor： Min Tao ,  Zhuowen Sun ,  Belgacem Haba ,  Hoki Kim ,  Wael Zohni ,  Shaowu Huang

IPC: H01L25/065 ,  H01L23/367 ,  H01L25/18 ,  H01L23/31 ,  H01L25/00 ,  H01L23/00

Abstract: Vertical memory modules enabled by fan-out redistribution layer(s) (RDLs) are provided. Memory dies may be stacked with each die having a signal pad directed to a sidewall of the die. A redistribution layer (RDL) is built on sidewalls of the stacked dies and coupled with the signal pads. The RDL may fan-out to UBM and solder balls, for example. An alternative process reconstitutes dies on a carrier with a first RDL on a front side of the dies. The dies and first RDL are encapsulated, and the modules vertically disposed for a second reconstitution on a second carrier. A second RDL is applied to exposed contacts of the vertically disposed modules and first RDLs. The vertical modules and second RDL are encapsulated in turn with a second mold material. The assembly may be singulated into individual memory modules, each with a fan-out RDL on the sidewalls of the vertically disposed dies.

公开(公告)号：US20180026011A1

公开(公告)日：2018-01-25

申请号：US15393100

申请日：2016-12-28

Applicant: Invensas Corporation

Inventor： Min Tao ,  Hoki Kim ,  Ashok S. Prabhu ,  Zhuowen Sun ,  Wael Zohni ,  Belgacem Haba

IPC: H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L21/52

CPC classification number: H01L25/0657 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/52 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/5283 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/09 ,  H01L24/46 ,  H01L24/49 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/071 ,  H01L25/105 ,  H01L25/112 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/02331 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/15151 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/19107

Abstract: Package-on-package (“PoP”) devices with same level wafer-level packaged (“WLP”) components and methods therefor are disclosed. In a PoP device, a first integrated circuit die is surface mount coupled to an upper surface of a package substrate. Conductive lines are coupled to the upper surface of the package substrate in a fan-out region. The first conductive lines extend away from the upper surface of the package substrate. A molding layer is formed over the upper surface of the package substrate, around sidewall surfaces of the first integrated circuit die, and around bases and shafts of the conductive lines. WLP microelectronic components are located at a same level above an upper surface of the molding layer respectively surface mount coupled to sets of upper portions of the conductive lines.

公开(公告)号：US09728524B1

公开(公告)日：2017-08-08

申请号：US15198615

申请日：2016-06-30

Applicant: Invensas Corporation

Inventor： Min Tao ,  Zhuowen Sun ,  Hoki Kim ,  Wael Zohni ,  Akash Agrawal

IPC: H01L23/49 ,  H01L23/31 ,  H01L21/56 ,  H01L25/10 ,  H01L25/065 ,  H01L23/498 ,  H01L25/00 ,  H05K1/18 ,  H05K1/11

CPC classification number: H01L25/105 ,  H01L23/49805 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2225/06589 ,  H05K1/11 ,  H05K1/181 ,  H05K2201/10378 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A microelectronic assembly includes a plurality of stacked microelectronic packages, each comprising a dielectric element having a major surface, an interconnect region adjacent an interconnect edge surface which extends away from the major surface, and plurality of package contacts at the interconnect region. A microelectronic element has a front surface with chip contacts thereon coupled to the package contacts, the front surface overlying and parallel to the major surface. The microelectronic packages are stacked with planes defined by the dielectric elements substantially parallel to one another, and the package contacts electrically coupled with panel contacts at a mounting surface of a circuit panel via an electrically conductive material, the planes defined by the dielectric elements being oriented at a substantial angle to the mounting surface.

公开(公告)号：US20210181511A1

公开(公告)日：2021-06-17

申请号：US17182016

申请日：2021-02-22

Applicant: Invensas Corporation

Inventor： Belgacem Haba ,  Ilyas Mohammed ,  Gabriel Z. Guevara ,  Min Tao

IPC: G02B27/01

Abstract: Apparatus and method relating generally to electronics are disclosed. In one such an apparatus, a film assembly has an upper surface and a lower surface opposite the upper surface. A dielectric film of the film assembly has a structured profile along the upper surface or the lower surface for having alternating ridges and grooves in a corrugated section in an at rest state of the film assembly. Conductive traces of the film assembly conform to the upper surface or the lower surface in or on the dielectric film in the corrugated section.

公开(公告)号：US20190273016A1

公开(公告)日：2019-09-05

申请号：US16136776

申请日：2018-09-20

Applicant: Invensas Corporation

Inventor： Belgacem Haba ,  Ilyas Mohammed ,  Gabriel Z. Guevara ,  Min Tao

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/302

Abstract: Apparatus and method relating generally to electronics are disclosed. In one such an apparatus, a film assembly has an upper surface and a lower surface opposite the upper surface. A dielectric film of the film assembly has a structured profile along the upper surface or the lower surface for having alternating ridges and grooves in a corrugated section in an at rest state of the film assembly. Conductive traces of the film assembly conform to the upper surface or the lower surface in or on the dielectric film in the corrugated section.

公开(公告)号：US10354976B2

公开(公告)日：2019-07-16

申请号：US15393068

申请日：2016-12-28

Applicant: Invensas Corporation

Inventor： Min Tao ,  Hoki Kim ,  Ashok S. Prabhu ,  Zhuowen Sun ,  Wael Zohni ,  Belgacem Haba

IPC: H01L21/48 ,  H01L25/065 ,  H01L21/52 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L25/00 ,  H01L23/528 ,  H01L25/07 ,  H01L25/11 ,  H01L23/538 ,  H01L25/10 ,  H01L25/18

Abstract: Dies-on-package devices and methods therefor are disclosed. In a dies-on-package device, a first IC die is surface mount coupled to an upper surface of a package substrate. Conductive lines are coupled to the upper surface of the package substrate in a fan-out region with respect to the first IC die. A molding layer is formed over the upper surface of the package substrate, around sidewall surfaces of the first IC die, and around bases and shafts of the conductive lines. A plurality of second IC dies is located at a same level above an upper surface of the molding layer respectively surface mount coupled to sets of upper portions of the conductive lines. The plurality of second IC dies are respectively coupled to the sets of the conductive lines in middle third portions respectively of the plurality of second IC dies for corresponding fan-in regions thereof.

公开(公告)号：US09991235B2

公开(公告)日：2018-06-05

申请号：US15393119

申请日：2016-12-28

Applicant: Invensas Corporation

Inventor： Min Tao ,  Hoki Kim ,  Ashok S. Prabhu ,  Zhuowen Sun ,  Wael Zohni ,  Belgacem Haba

IPC: H01L25/07 ,  H01L25/00 ,  H01L23/31 ,  H01L23/00 ,  H01L23/528 ,  H01L25/11 ,  H01L21/56

CPC classification number: H01L25/0657 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/52 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/5283 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/09 ,  H01L24/46 ,  H01L24/49 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/071 ,  H01L25/105 ,  H01L25/112 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/02331 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/15151 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/19107

Abstract: Package-on-package (“PoP”) devices with upper RDLs of WLP (“WLP”) components and methods therefor are disclosed. In a PoP device, a first IC die is surface mount coupled to an upper surface of the package substrate. Conductive lines are coupled to the upper surface of the package substrate in a fan-out region with reference to the first IC. A molding layer is formed over the upper surface of the package substrate. A first and a second WLP microelectronic component is located at a same level above an upper surface of the molding layer respectively surface mount coupled to sets of upper portions of the conductive lines. Each of the first and the second WLP microelectronic components have a second IC die located below a first RDL respectively thereof. A third and a fourth IC die are respectively surface mount coupled over the first and the second WLP microelectronic components.

公开(公告)号：US20180025987A1

公开(公告)日：2018-01-25

申请号：US15393048

申请日：2016-12-28

Applicant: Invensas Corporation

Inventor： Min Tao ,  Hoki Kim ,  Ashok S. Prabhu ,  Zhuowen Sun ,  Wael Zohni ,  Belgacem Haba

IPC: H01L23/538 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L25/10

CPC classification number: H01L25/0657 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/52 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/5283 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/09 ,  H01L24/46 ,  H01L24/49 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/071 ,  H01L25/105 ,  H01L25/112 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/02331 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/15151 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/19107

Abstract: Wafer-level packaged components are disclosed. In a wafer-level-packaged, an integrated circuit die has first contacts in an inner third region of a surface of the integrated circuit die. A redistribution layer has second contacts in an inner third region of a first surface of the redistribution layer and third contacts in an outer third region of a second surface of the redistribution layer opposite the first surface thereof. The second contacts of the redistribution layer are coupled for electrical conductivity to the first contacts of the integrated circuit die with the surface of the integrated circuit die face-to-face with the first surface of the redistribution layer. The third contacts are offset from the second contacts for being positioned in a fan-out region for association at least with the outer third region of the second surface of the redistribution layer, the third contacts being surface mount contacts.

公开(公告)号：US20210288037A1

公开(公告)日：2021-09-16

申请号：US17327169

申请日：2021-05-21

Applicant: Invensas Corporation

Inventor： Min Tao ,  Liang Wang ,  Rajesh Katkar ,  Cyprian Emeka Uzoh

IPC: H01L25/16 ,  H01L33/00 ,  H01L25/10 ,  H01L27/12 ,  H01L27/15 ,  H01L25/18 ,  H01L21/321 ,  H01L21/02 ,  H01L23/00

Abstract: Direct-bonded LED arrays and applications are provided. An example process fabricates a LED structure that includes coplanar electrical contacts for p-type and n-type semiconductors of the LED structure on a flat bonding interface surface of the LED structure. The coplanar electrical contacts of the flat bonding interface surface are direct-bonded to electrical contacts of a driver circuit for the LED structure. In a wafer-level process, micro-LED structures are fabricated on a first wafer, including coplanar electrical contacts for p-type and n-type semiconductors of the LED structures on the flat bonding interface surfaces of the wafer. At least the coplanar electrical contacts of the flat bonding interface are direct-bonded to electrical contacts of CMOS driver circuits on a second wafer. The process provides a transparent and flexible micro-LED array display, with each micro-LED structure having an illumination area approximately the size of a pixel or a smallest controllable element of an image represented on a high-resolution video display.