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公开(公告)号:US08902147B2
公开(公告)日:2014-12-02
申请号:US14143655
申请日:2013-12-30
Inventor: Yoshihiro Kotani , Mitsuru Goto
CPC classification number: G09G3/3677 , G11C19/184 , G11C19/28
Abstract: A gate signal line driving circuit and a display device which can suppress the degradation of an element attributed to the use of the element for a long time, and can realize the prolongation of lifetime of the element are provided. With respect to elements to which a HIGH voltage is applied for a long time, a plurality of elements are connected in parallel, and at least some of the plurality of elements are driven by switching elements.
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公开(公告)号:US09811189B2
公开(公告)日:2017-11-07
申请号:US14732237
申请日:2015-06-05
Applicant: Japan Display Inc.
Inventor: Yoshihiro Kotani , Hiroshi Mizuhashi , Hayato Kurasawa , Kohei Azumi
IPC: G06F3/041 , G06F3/044 , G09G3/36 , G02F1/1333
CPC classification number: G06F3/0412 , G02F1/13338 , G06F3/0416 , G06F3/044 , G09G3/3614 , G09G3/3648 , G09G3/3688 , G09G2310/0291 , G09G2310/08 , G09G2354/00
Abstract: A display device comprises gate lines extending in a first direction, drain lines extending in a second direction, common electrodes extending in the second direction, and a drive circuit. The common electrodes are configured to be partitioned over drain lines of pixels of a specific color and to be used also as touch panel scan electrodes. The drive circuit is configured so that write periods for driving the gate lines and touch sensing periods for driving the scan electrodes are alternately repeated in each frame period, signal polarity of drain lines for colors other than the specific color is inverted every frame, signal polarity of drain lines for the specific color is inverted at a cycle shorter than one frame, and the cycle of the signal polarity inversion of the drain lines for the specific color can be changed.
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公开(公告)号:US09793007B2
公开(公告)日:2017-10-17
申请号:US15090664
申请日:2016-04-05
Applicant: Japan Display Inc.
Inventor: Takahiro Ochiai , Mitsuru Goto , Hiroyuki Higashijima , Yoshihiro Kotani , Shuuichirou Matsumoto
CPC classification number: G11C19/287 , G09G3/3677 , G09G5/003 , G09G2310/0286 , G09G2310/08 , G09G2330/021
Abstract: A bidirectional shift register capable of performing a stable shift operation in both directions and an image display device using the same are provided. In forward shift operation, when reference point N1 is at H level, (n+4)-th unit register circuit as a rear stage of the bidirectional shift register outputs pulse G(n+4) in synchronization with clock pulse V(n+4) inputted to (n+4)-th unit register circuit. A backward direction trigger signal VSTB is generated not only at the time of start of backward shift, but also, for example, in period (time t4 to t5) of one-phase clock immediately after G(n+4) is outputted in vertical blanking interval of the forward shift. The backward direction trigger signal VSTB is inputted to gate of a transistor provided to set reference point N1 of (n+4)-th unit register circuit to H level at the time of start of the backward shift.
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公开(公告)号:US09111474B2
公开(公告)日:2015-08-18
申请号:US13629813
申请日:2012-09-28
Applicant: Japan Display Inc.
Inventor: Youichi Ooki , Yoshihiro Kotani
CPC classification number: G09G5/001 , G09G3/3611 , G09G2370/04 , G09G2370/14
Abstract: A method of terminating a pair of transmission lines is changed over by terminal setting. Display data is supplied to a master drive circuit and (n−1)-pieces of drive circuits from a host computer via the pair of transmission lines in accordance with a differential serial transmission system. Each drive circuit includes an SELC terminal. When a voltage inputted to the SELC terminal is at a first voltage level, a resistor having a resistance value of Ra is connected between the pair of transmission lines in the master drive circuit thus terminating the pair of transmission lines, and the pair of transmission lines in the slave drive circuits is opened. When the voltage inputted to the SELC terminal is at a second voltage level which differs from the first voltage level, a resistor having a resistance value of (n×Ra) is connected between the pair of transmission lines.
Abstract translation: 通过终端设置来切换一对终端传输线路的方法。 根据差分串行传输系统,通过一对传输线将显示数据提供给主驱动电路和(n-1)个来自主计算机的驱动电路。 每个驱动电路包括一个SELC终端。 当输入到SELC端子的电压处于第一电压电平时,具有电阻值Ra的电阻器连接在主驱动电路中的一对传输线之间,从而终止一对传输线,并且一对传输线 在从驱动电路中打开。 当输入到SELC端子的电压处于与第一电压电平不同的第二电压电平时,在一对传输线之间连接具有电阻值(n×Ra)的电阻器。
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公开(公告)号:US08766965B2
公开(公告)日:2014-07-01
申请号:US13921755
申请日:2013-06-19
Inventor: Kenichi Akiyama , Yoshihiro Kotani , Hiroko Sehata , Kouichi Kotera
IPC: G06F3/038
CPC classification number: G09G3/20 , G02F1/13306 , G09G3/36
Abstract: A drive circuit of a display device includes decoder circuit which outputs a voltage based on a 8-bit digital value. The decoder circuit includes a first decoder circuit and a second decoder circuit which output one voltage respectively using upper-order 6 bits of the 8-bit digital value; a selection circuit which receives voltages outputted from the first decoder circuit and the second decoder circuit, and distributes the two voltages to three terminals; and an intermediate voltage output circuit which outputs an intermediate voltage which is a one of five kinds of values based on the three voltages. The first decoder circuit and the second decoder circuit respectively include a select-switch-type decoder circuit and a tournament-type decoder circuit.
Abstract translation: 显示装置的驱动电路包括基于8位数字值输出电压的解码器电路。 解码器电路包括分别使用8位数字值的高位6位输出一个电压的第一解码器电路和第二解码器电路; 接收从第一解码器电路和第二解码器电路输出的电压并将两个电压分配给三个端子的选择电路; 以及中间电压输出电路,其基于三个电压输出作为五种值中的一种的中间电压。 第一解码器电路和第二解码器电路分别包括选择开关型解码器电路和比赛型解码器电路。
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