公开(公告)号：US11443721B2

公开(公告)日：2022-09-13

申请号：US16738537

申请日：2020-01-09

Applicant: Japan Display Inc.

Inventor： Masaya Tamaki ,  Yutaka Mitsuzawa ,  Takayuki Nakao ,  Yutaka Ozawa

IPC: G09G5/395 ,  G09G3/36

Abstract: A display device includes: sub-pixels each including a memory block including memories; memory selection line groups each including memory selection lines electrically coupled to the memory blocks in the sub-pixels that belong to the corresponding row; a memory selection circuit configured to concurrently output memory selection signals to the memory selection line groups; a potential line; a conduction switch provided for at least one memory in the memory block on a one-to-one basis; and an operating-memory conduction circuit configured to output, to the conduction switch, an operation signal for determining whether to electrically couple or uncouple the potential line and the corresponding one memory. Each memory is capable of storing sub-pixel data therein when being coupled to the potential line. Each sub-pixel displays an image based on the sub-pixel data stored in one memory in the sub-pixel according to the memory selection line supplied with the memory selection signal.

公开(公告)号：US11158277B2

公开(公告)日：2021-10-26

申请号：US16872771

申请日：2020-05-12

Applicant: Japan Display Inc.

Inventor： Yutaka Mitsuzawa ,  Takayuki Nakao ,  Masaya Tamaki ,  Yutaka Ozawa

IPC: G09G3/36 ,  G09G3/32

Abstract: A display device includes: a plurality of sub-pixels each including a memory block that includes a plurality of memories each of which is configured to store sub-pixel data; a plurality of memory selection line groups provided to respective rows and each including a plurality of memory selection lines electrically coupled to the corresponding memory blocks in the sub-pixels that belong to a corresponding row; a memory selection circuit configured to simultaneously output a memory selection signal to the memory selection line groups, the memory selection signal being a signal for selecting one from the plurality of memories in each of the memory blocks. In accordance with the memory selection lines supplied with the memory selection signal, the sub-pixels display an image based on the sub-pixel data stored in memories in the respective sub-pixels, the memories each being one of the plurality of memories in the corresponding sub-pixel.

公开(公告)号：US10692455B2

公开(公告)日：2020-06-23

申请号：US15949556

申请日：2018-04-10

Applicant: Japan Display Inc.

Inventor： Yutaka Mitsuzawa ,  Takayuki Nakao ,  Masaya Tamaki ,  Yutaka Ozawa

IPC: G09G3/36 ,  G09G3/32

Abstract: A display device includes: a plurality of sub-pixels each including a memory block that includes a plurality of memories each of which is configured to store sub-pixel data; a plurality of memory selection line groups provided to respective rows and each including a plurality of memory selection lines electrically coupled to the corresponding memory blocks in the sub-pixels that belong to a corresponding row; a memory selection circuit configured to simultaneously output a memory selection signal to the memory selection line groups, the memory selection signal being a signal for selecting one from the plurality of memories in each of the memory blocks. In accordance with the memory selection lines supplied with the memory selection signal, the sub-pixels display an image based on the sub-pixel data stored in memories in the respective sub-pixels, the memories each being one of the plurality of memories in the corresponding sub-pixel.

公开(公告)号：US10565951B2

公开(公告)日：2020-02-18

申请号：US15161933

申请日：2016-05-23

Applicant: Japan Display Inc.

Inventor： Fumitaka Gotoh ,  Isao Edatsune ,  Yutaka Ozawa ,  Tsutomu Harada

IPC: G09G3/36

Abstract: According to an aspect, a display device includes: a display area provided to a substrate; a shift register including a plurality of registers coupled in series; and a control circuit that supplies clock pulses to the registers, and that supplies a start pulse to a first register of the shift register to acquire an output from a last register of the shift register, wherein the display area is provided in an area surrounded by the shift register, the control circuit, and wiring that couples the shift register to the control circuit.

公开(公告)号：US10559286B2

公开(公告)日：2020-02-11

申请号：US16057934

申请日：2018-08-08

Applicant: Japan Display Inc.

Inventor： Masaya Tamaki ,  Yutaka Mitsuzawa ,  Takayuki Nakao ,  Yutaka Ozawa

IPC: G09G5/395 ,  G09G3/36

Abstract: A display device includes: sub-pixels each including a memory block including memories; memory selection line groups each including memory selection lines electrically coupled to the memory blocks in the sub-pixels that belong to the corresponding row; a memory selection circuit configured to concurrently output memory selection signals to the memory selection line groups; a potential line; a conduction switch provided for at least one memory in the memory block on a one-to-one basis; and an operating-memory conduction circuit configured to output, to the conduction switch, an operation signal for determining whether to electrically couple or uncouple the potential line and the corresponding one memory. Each memory is capable of storing sub-pixel data therein when being coupled to the potential line. Each sub-pixel displays an image based on the sub-pixel data stored in one memory in the sub-pixel according to the memory selection line supplied with the memory selection signal.

公开(公告)号：US20180308446A1

公开(公告)日：2018-10-25

申请号：US15949556

申请日：2018-04-10

Applicant: Japan Display Inc.

Inventor： Yutaka Mitsuzawa ,  Takayuki Nakao ,  Masaya Tamaki ,  Yutaka Ozawa

IPC: G09G3/36

Abstract: A display device includes: a plurality of sub-pixels each including a memory block that includes a plurality of memories each of which is configured to store sub-pixel data; a plurality of memory selection line groups provided to respective rows and each including a plurality of memory selection lines electrically coupled to the corresponding memory blocks in the sub-pixels that belong to a corresponding row; a memory selection circuit configured to simultaneously output a memory selection signal to the memory selection line groups, the memory selection signal being a signal for selecting one from the plurality of memories in each of the memory blocks. In accordance with the memory selection lines supplied with the memory selection signal, the sub-pixels display an image based on the sub-pixel data stored in memories in the respective sub-pixels, the memories each being one of the plurality of memories in the corresponding sub-pixel.