-
11.发明申请公开(公告)号：US20250036503A1
公开(公告)日：2025-01-30
申请号：US18916370
申请日：2024-10-15
Applicant: Mellanox Technologies, Ltd.
Inventor： Natan Manevich , Dotan David Levi , Shay Aisman , Ariel Almog , Ran Avraham Koren
IPC: G06F11/07
Abstract: A method includes presenting, by a processing device, in a user interface of a display device, a set of menu items associated with a plurality of criteria and detecting one or more input signals from one or more selections of the set of menu items. The method includes creating a command that includes one or more criteria corresponding to selected options of the plurality of criteria derived from the one or more input signals. The method includes sending, by the processing device, the command to a network adapter device to trigger a polling operation to be performed that causes internal logic of the network adapter device to sample event data associated with a latency of data packets sent by a hardware process that is specific to the one or more criteria.
-
12.发明授权公开(公告)号：US12158795B2
公开(公告)日：2024-12-03
申请号：US18074751
申请日：2022-12-05
Applicant: Mellanox Technologies, Ltd.
Inventor： Natan Manevich , Dotan David Levi , Shay Aisman , Ariel Almog , Ran Avraham Koren
Abstract: A device includes a hardware block to perform a hardware process and internal logic coupled between a processing device, which executes instructions, and the hardware block. The internal logic can one of measure execution time or count clock cycles of at least a portion of the hardware process. The internal logic can further, in response to the measured execution time or the counted clock cycles satisfying a predetermined condition, provide data associated with the one of the execution time measurement or the clock cycles count to the processing device, the data being statistically indicative of a latency of data packets sent by the hardware process over a total time the hardware process executes.
-
13.发明公开公开(公告)号：US20240289288A1
公开(公告)日：2024-08-29
申请号：US18655386
申请日：2024-05-06
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Daniel Marcovitch , Eliav Bar-Ilan , Ran Avraham Koren , Liran Liss , Oren Duer , Shahaf Shuler
CPC classification number: G06F13/28 , G06F13/4221 , G06F2213/0024
Abstract: A network adapter includes a network interface, a bus interface, a hardware-implemented data-path and a programmable Data-Plane Accelerator (DPA). The network interface is to communicate with a network. The bus interface is to communicate with an external device over a peripheral bus. The hardware-implemented data-path includes a plurality of packet-processing engines to process data units exchanged between the network and the external device. The DPA is to expose on the peripheral bus a User-Defined Peripheral-bus Device (UDPD), to run user-programmable logic that implements the UDPD, and to process transactions issued from the external device to the UDPD by reusing one or more of the packet-processing engines of the data-path.
-
14.发明授权公开(公告)号：US12007921B2
公开(公告)日：2024-06-11
申请号：US17979013
申请日：2022-11-02
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Daniel Marcovitch , Eliav Bar-Ilan , Ran Avraham Koren , Liran Liss , Oren Duer , Shahaf Shuler
CPC classification number: G06F13/28 , G06F13/4221 , G06F2213/0024
Abstract: A network adapter includes a network interface, a bus interface, a hardware-implemented data-path and a programmable Data-Plane Accelerator (DPA). The network interface is to communicate with a network. The bus interface is to communicate with an external device over a peripheral bus. The hardware-implemented data-path includes a plurality of packet-processing engines to process data units exchanged between the network and the external device. The DPA is to expose on the peripheral bus a User-Defined Peripheral-bus Device (UDPD), to run user-programmable logic that implements the UDPD, and to process transactions issued from the external device to the UDPD by reusing one or more of the packet-processing engines of the data-path.
-
-
-
Search Results
14
records
(took 0.026 seconds)
