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公开(公告)号：JP2006202482A
公开(公告)日：2006-08-03
申请号：JP2006065104
申请日：2006-03-10
Inventor： KEETH BRENT , BUNKER LAYNE G , DERNER SCOTT J , TAYLOR RONALD L , MULLIN JOHN S , BEFFA RAYMOND J , ROSS FRANK F , KINSMAN LARRY D
IPC: G11C11/401 , G11C11/409 , G11C5/02 , G11C5/06 , G11C11/407 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C29/04 , G11C29/14 , H01L21/8242 , H01L27/108 , H03K19/0175
CPC classification number: G11C5/063 , G11C5/025 , G11C5/145 , G11C5/147 , G11C11/401 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C11/4099 , G11C29/021 , G11C29/028 , G11C29/12 , G11C29/12005 , G11C29/46 , G11C29/787 , G11C2029/0407 , H01L27/10805 , H01L2224/4826 , H01L2224/73215 , H01L2924/1305 , H01L2924/13091 , H01L2924/00
Abstract: PROBLEM TO BE SOLVED: To reduce a load current with respect to a boosted voltage by an output buffer. SOLUTION: The output buffer circuit is provided with a plurality of output drive transistors serially connected between a first voltage source and an earth, an output terminal which responds to the serially connected output drive transistor, a latch for receiving data output to the output terminal, a logical circuit for controlling the output drive transistor to drive the voltage of the output terminal at a high or low potential indicating the logical state of the output data in response to the latch, a boot capacitor for supplying additional voltages to some output drive transistors, a holding transistor for connecting the boost capacitor to a second voltage source in response to the logical circuit, and a self-timer type circuit path connected between the holding transistor and the boot capacitor. COPYRIGHT: (C)2006,JPO&NCIPI
Abstract translation: 要解决的问题：通过输出缓冲器减小相对于升压电压的负载电流。 解决方案：输出缓冲器电路设置有串联连接在第一电压源和地之间的多个输出驱动晶体管，响应于串联输出驱动晶体管的输出端，用于接收数据输出到 输出端子，用于控制输出驱动晶体管的逻辑电路，用于响应于锁存器而将输出端子的电压驱动为指示输出数据的逻辑状态的高电位或低电位，用于向某些输出提供附加电压的引导电容器 驱动晶体管，用于响应于逻辑电路将升压电容器连接到第二电压源的保持晶体管，以及连接在保持晶体管和引导电容器之间的自拍定时器型电路。 版权所有（C）2006，JPO＆NCIPI
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公开(公告)号：JP2006190470A
公开(公告)日：2006-07-20
申请号：JP2006062269
申请日：2006-03-08
Inventor： KEETH BRENT , BUNKER LAYNE G , DERNER SCOTT J , TAYLOR RONALD L , MULLIN JOHN S , BEFFA RAYMOND J , ROSS FRANK F , KINSMAN LARRY D
IPC: G11C11/401 , G11C11/409 , G11C5/02 , G11C5/06 , G11C11/407 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C29/04 , G11C29/14 , H01L21/8242 , H01L27/108
CPC classification number: G11C5/063 , G11C5/025 , G11C5/145 , G11C5/147 , G11C11/401 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C11/4099 , G11C29/021 , G11C29/028 , G11C29/12 , G11C29/12005 , G11C29/46 , G11C29/787 , G11C2029/0407 , H01L27/10805 , H01L2224/4826 , H01L2224/73215 , H01L2924/1305 , H01L2924/13091 , H01L2924/00
Abstract: PROBLEM TO BE SOLVED: To provide a memory having various input/output sizes. SOLUTION: The dynamic random access memory is a plurality of individual arrays consisting of memory cells, and the memory is provided with a plurality of individual array forming a plurality of array blocks, a plurality of sense amplifiers arranged between adjacent rows of the individual arrays in the array block, a plurality of peripheral apparatus having a plurality of row decoders arranged between adjacent rows of the individual arrays in the array block, and a plurality of voltage sources generating a plurality of supply voltage used by the array block and a plurality of peripheral apparatus. The plurality of individual arrays have a digit line, the array block has an I/O line, the sense amplifier has a circuit transmitting a signal on the digit line to the I/O line. The array block includes a plurality of data lines forming the I/O line and a cross part, the plurality of peripheral circuits include a plurality of multiplexers transmitting a signal on the I/O line to the data line. COPYRIGHT: (C)2006,JPO&NCIPI
Abstract translation: 要解决的问题：提供具有各种输入/输出尺寸的存储器。 解决方案：动态随机存取存储器是由存储器单元组成的多个单独阵列，并且存储器设置有形成多个阵列块的多个单独阵列，多个读出放大器布置在相邻行之间 阵列块中的各个阵列，多个外围设备，其具有布置在阵列块中的各个阵列的相邻行之间的多个行解码器，以及多个电压源，其产生阵列块使用的多个电源电压，以及 多个外围设备。 多个单独阵列具有数字线，阵列块具有I / O线，读出放大器具有将数字线上的信号发送到I / O线的电路。 阵列块包括形成I / O线的多条数据线和交叉部分，多个外围电路包括将I / O线上的信号发送到数据线的多个复用器。 版权所有（C）2006，JPO＆NCIPI
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公开(公告)号：JP2006252757A
公开(公告)日：2006-09-21
申请号：JP2006065623
申请日：2006-03-10
Inventor： KEETH BRENT , BUNKER LAYNE G , DERNER SCOTT J , TAYLOR RONALD L , MULLIN JOHN S , BEFFA RAYMOND J , ROSS FRANK F , KINSMAN LARRY D
IPC: G11C11/401 , G11C5/02 , G11C5/06 , G11C11/407 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C29/04 , G11C29/14 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/108
CPC classification number: G11C5/063 , G11C5/025 , G11C5/145 , G11C5/147 , G11C11/401 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C11/4099 , G11C29/021 , G11C29/028 , G11C29/12 , G11C29/12005 , G11C29/46 , G11C29/787 , G11C2029/0407 , H01L27/10805 , H01L2224/4826 , H01L2224/73215 , H01L2924/1305 , H01L2924/13091 , H01L2924/00
Abstract: PROBLEM TO BE SOLVED: To provide an electrically conductive layer which goes through between the adjacent columns of a plurality of independent arrays in order to mutually connect peripheral devices or the like. SOLUTION: The dynamic random access memory is provided with: an array of memory cells; a plurality of peripheral devices which write data into the array of the memory cells and read data from the array of the memory cells and include a plurality of multiplexer cells that are programmable; a power supply; a plurality of pads; and an electrically conductive layer which mutually connects between a plurality of memory cells, the plurality of peripheral devices, the power supply and the plurality of pads. The array of the memory cells are arranged in rows and columns to form a plurality of independent arrays. The plurality of independent arrays are constituted into a plurality of array blocks. The plurality of peripheral devices have a plurality of sense amplifiers arranged between the adjacent rows of the independent arrays and a plurality of row decoders arranged between the adjacent columns of the independent arrays. COPYRIGHT: (C)2006,JPO&NCIPI
Abstract translation: 要解决的问题：为了提供在多个独立阵列的相邻列之间穿过的导电层，以便相互连接外围设备等。 解决方案：动态随机存取存储器具有：一组存储单元; 多个外围设备，其将数据写入存储器单元的阵列并从存储器单元的阵列读取数据，并且包括可编程的多个多路复用器单元; 电源; 多个垫; 以及在多个存储单元，多个外围设备，电源和多个焊盘之间相互连接的导电层。 存储单元的阵列以行和列排列以形成多个独立的阵列。 多个独立阵列构成多个阵列块。 多个外围设备具有布置在独立阵列的相邻行之间的多个读出放大器和布置在独立阵列的相邻列之间的多个行解码器。 版权所有（C）2006，JPO＆NCIPI
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公开(公告)号：JP2006228418A
公开(公告)日：2006-08-31
申请号：JP2006065169
申请日：2006-03-10
Inventor： KEETH BRENT , BUNKER LAYNE G , DERNER SCOTT J , TAYLOR RONALD L , MULLIN JOHN S , BEFFA RAYMOND J , ROSS FRANK F , KINSMAN LARRY D
IPC: G11C11/401 , G11C5/02 , G11C5/06 , G11C11/407 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C29/04 , G11C29/14 , H01L21/8242 , H01L27/108
CPC classification number: G11C5/063 , G11C5/025 , G11C5/145 , G11C5/147 , G11C11/401 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C11/4099 , G11C29/021 , G11C29/028 , G11C29/12 , G11C29/12005 , G11C29/46 , G11C29/787 , G11C2029/0407 , H01L27/10805 , H01L2224/4826 , H01L2224/73215 , H01L2924/1305 , H01L2924/13091 , H01L2924/00
Abstract: PROBLEM TO BE SOLVED: To supply an optimum internal voltage to a large memory chip in accordance with operation. SOLUTION: The dynamic random access memory has a plurality of independent arrays composed of memory cells, the independent arrays have digit lines extended through the array, the independent arrays are arranged in rows and columns and form a plurality of array blocks, has a plurality of peripheral equipment performing write-in of data and read-out of data for the memory cell using the digit line, and has a power source generating a plurality of supply voltages, which has a plurality of generators generating bias voltages biasing the digit lines and the number of generators is the same as the number of array blocks, and has a power distribution bus sypplying the plurality of supply voltages to the plurality of array blocks and peripheral equipment. COPYRIGHT: (C)2006,JPO&NCIPI
Abstract translation: 要解决的问题：根据操作向大型存储芯片提供最佳内部电压。 解决方案：动态随机存取存储器具有由存储器单元组成的多个独立阵列，独立阵列具有通过阵列延伸的数字线，独立阵列以行和列排列并形成多个阵列块，具有 多个外围设备使用数字线执行数据的写入和存储单元的数据的读出，并且具有产生多个电源电压的电源，该电源电压具有产生偏置电压的多个发生器 线路和发电机的数量与阵列块的数量相同，并且具有向多个阵列块和外围设备施加多个电源电压的配电总线。 版权所有（C）2006，JPO＆NCIPI
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公开(公告)号：JP2006203239A
公开(公告)日：2006-08-03
申请号：JP2006065515
申请日：2006-03-10
Inventor： KEETH BRENT , BUNKER LAYNE G , DERNER SCOTT J , TAYLOR RONALD L , MULLIN JOHN S , BEFFA RAYMOND J , ROSS FRANK F , KINSMAN LARRY D
IPC: G11C11/401 , H01L23/50 , G11C5/02 , G11C5/06 , G11C11/407 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C29/04 , G11C29/14 , H01L21/56 , H01L21/8242 , H01L27/108
CPC classification number: G11C5/063 , G11C5/025 , G11C5/145 , G11C5/147 , G11C11/401 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C11/4099 , G11C29/021 , G11C29/028 , G11C29/12 , G11C29/12005 , G11C29/46 , G11C29/787 , G11C2029/0407 , H01L27/10805 , H01L2224/4826 , H01L2224/73215 , H01L2924/1305 , H01L2924/13091 , H01L2924/00
Abstract: PROBLEM TO BE SOLVED: To provide a method for sealing a solid state device in a design of a dynamic random access memory (DRAM) which is an integrated circuit memory. SOLUTION: The method is provided for sealing the solid state device in which a lead frame is connected to a joint pad. In the method, a tie bar serves as a holder for a lead finger under sealing treatment. It is preferable that a part of the lead frame forms a part of an electric circuit of the solid state device. Moreover it is preferable that the method includes a process for cutting the tie bar. COPYRIGHT: (C)2006,JPO&NCIPI
Abstract translation: 要解决的问题：提供一种在作为集成电路存储器的动态随机存取存储器（DRAM）的设计中密封固态器件的方法。 解决方案：该方法用于将引线框架连接到接合垫的固态器件进行密封。 在该方法中，连杆用作密封处理下的铅指的保持器。 优选地，引线框架的一部分形成固态器件的电路的一部分。 此外，优选的是，该方法包括用于切割连杆的方法。 版权所有（C）2006，JPO＆NCIPI
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Patent Agency Ranking
公开(公告)号：JP2006202486A
公开(公告)日：2006-08-03
申请号：JP2006065570
申请日：2006-03-10
Inventor： KEETH BRENT , BUNKER LAYNE G , DERNER SCOTT J , TAYLOR RONALD L , MULLIN JOHN S , BEFFA RAYMOND J , ROSS FRANK F , KINSMAN LARRY D
IPC: G11C11/401 , G11C29/14 , G11C5/02 , G11C5/06 , G11C11/407 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C29/04 , H01L21/8242 , H01L27/108
CPC classification number: G11C5/063 , G11C5/025 , G11C5/145 , G11C5/147 , G11C11/401 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C11/4099 , G11C29/021 , G11C29/028 , G11C29/12 , G11C29/12005 , G11C29/46 , G11C29/787 , G11C2029/0407 , H01L27/10805 , H01L2224/4826 , H01L2224/73215 , H01L2924/1305 , H01L2924/13091 , H01L2924/00
Abstract: PROBLEM TO BE SOLVED: To solve the problem that it is difficult to determine whether a memory integrated circuit has successfully completed a test mode. SOLUTION: The method includes a step of inputting a series of control signals to a solid state device, a step of inputting a voltage outside a voltage range used for indicating a logical signal to the solid state device, a step of inputting at least one address to the solid state device, and a step of decoding an address to check test mode information. The step of inputting the voltage to the solid state device preferably includes a step of inputting a voltage higher than a highest voltage used for indicating a logical signal in the solid state device. The step of inputting at least one address to the solid state device is preferably executed during the step of inputting the voltage. COPYRIGHT: (C)2006,JPO&NCIPI
Abstract translation: 要解决的问题：为了解决难以确定存储器集成电路是否已经成功完成测试模式的问题。 解决方案：该方法包括将一系列控制信号输入到固态设备的步骤，将用于指示逻辑信号的电压范围外的电压输入到固态设备的步骤，在 至少一个地址到固态设备，以及解码地址以检查测试模式信息的步骤。 向固态器件输入电压的步骤最好包括在固态器件中输入高于用于指示逻辑信号的最高电压的电压的步骤。 优选在输入电压的步骤期间执行向固态设备输入至少一个地址的步骤。 版权所有（C）2006，JPO＆NCIPI
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公开(公告)号：JP2006202483A
公开(公告)日：2006-08-03
申请号：JP2006065136
申请日：2006-03-10
Inventor： KEETH BRENT , BUNKER LAYNE G , DERNER SCOTT J , TAYLOR RONALD L , MULLIN JOHN S , BEFFA RAYMOND J , ROSS FRANK F , KINSMAN LARRY D
IPC: G11C11/401 , G11C11/409 , G11C5/02 , G11C5/06 , G11C11/407 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C29/04 , G11C29/14 , H01L21/8242 , H01L27/108
CPC classification number: G11C5/063 , G11C5/025 , G11C5/145 , G11C5/147 , G11C11/401 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C11/4099 , G11C29/021 , G11C29/028 , G11C29/12 , G11C29/12005 , G11C29/46 , G11C29/787 , G11C2029/0407 , H01L27/10805 , H01L2224/4826 , H01L2224/73215 , H01L2924/1305 , H01L2924/13091 , H01L2924/00
Abstract: PROBLEM TO BE SOLVED: To reduce a load with respect to the boost power source of an output buffer. SOLUTION: A method for controlling the charging of a boot capacitor in the output buffer of a memory device includes a step of charging the boot capacitor from a voltage power source to a predetermined voltage, a step of holding the boot capacitor at a predetermined voltage, a step of supplying the charges of the boot capacitor to a pull-up transistor when the pull-up transistor is conductive, a step of disconnecting the boot capacitor and the voltage source from each other when the pull-up transistor is conductive, a step of monitoring the disconnecting step, and a step of unbooting the boot capacitor after the boot capacitor is disconnected from the voltage source. The monitoring step includes a step of sensing the holding transistor used for connecting the boot capacitor to a predetermined voltage. COPYRIGHT: (C)2006,JPO&NCIPI
Abstract translation: 要解决的问题：减少相对于输出缓冲器的升压电源的负载。 解决方案：一种用于控制存储器件的输出缓冲器中的引导电容器的充电的方法，包括将引导电容器从电压电源充电到预定电压的步骤，将保护电容器保持在 预定电压，当上拉晶体管导通时将引导电容器的电荷提供给上拉晶体管的步骤;当上拉晶体管导通时将引导电容器和电压源彼此断开的步骤 ，监视断开步骤的步骤，以及在引导电容器与电压源断开之后解除引导电容器的步骤。 监视步骤包括将用于将引导电容器连接到预定电压的保持晶体管的步骤。 版权所有（C）2006，JPO＆NCIPI
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公开(公告)号：JP2006202479A
公开(公告)日：2006-08-03
申请号：JP2006062076
申请日：2006-03-08
Inventor： KEETH BRENT , BUNKER LAYNE G , DERNER SCOTT J , TAYLOR RONALD L , MULLIN JOHN S , BEFFA RAYMOND J , ROSS FRANK F , KINSMAN LARRY D
IPC: G11C11/401 , G11C11/407 , G11C5/02 , G11C5/06 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C29/04 , G11C29/14 , H01L21/8242 , H01L27/108
CPC classification number: G11C5/063 , G11C5/025 , G11C5/145 , G11C5/147 , G11C11/401 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C11/4099 , G11C29/021 , G11C29/028 , G11C29/12 , G11C29/12005 , G11C29/46 , G11C29/787 , G11C2029/0407 , H01L27/10805 , H01L2224/4826 , H01L2224/73215 , H01L2924/1305 , H01L2924/13091 , H01L2924/00
Abstract: PROBLEM TO BE SOLVED: To reduce the number of power amplifiers by this control as all the power amplifier are not turned OF/ON at once but properly controlled by a group. SOLUTION: A voltage regulator for the dynamic random access memory having an array divided into array blocks is provided with a voltage reference circuit for generating a reference voltage, a plurality of power amplifiers some of which are arranged to supply power to some array blocks and which amplify supply voltages, and a control circuit for turning the power amplifier to an operation inhibited state when the array block connected to the power amplifier is in an operation inhibited state. COPYRIGHT: (C)2006,JPO&NCIPI
Abstract translation: 要解决的问题：通过该控制来减少功率放大器的数量，因为所有的功率放大器不是立即转换为OF / ON，而是被组合适当地控制。 解决方案：用于具有划分成阵列块的阵列的动态随机存取存储器的电压调节器设置有用于产生参考电压的电压参考电路，多个功率放大器，其中一些功率放大器被布置为向某些阵列供电 块，并且放大电源电压;以及控制电路，用于当连接到功率放大器的阵列块处于操作禁止状态时将功率放大器转到操作禁止状态。 版权所有（C）2006，JPO＆NCIPI
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公开(公告)号：JP2006202478A
公开(公告)日：2006-08-03
申请号：JP2006062044
申请日：2006-03-08
Inventor： KEETH BRENT , BUNKER LAYNE G , DERNER SCOTT J , TAYLOR RONALD L , MULLIN JOHN S , BEFFA RAYMOND J , ROSS FRANK F , KINSMAN LARRY D
IPC: G11C11/401 , G11C11/407 , G11C5/02 , G11C5/06 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C29/04 , G11C29/14 , H01L21/8242 , H01L27/108
CPC classification number: G11C5/063 , G11C5/025 , G11C5/145 , G11C5/147 , G11C11/401 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C11/4099 , G11C29/021 , G11C29/028 , G11C29/12 , G11C29/12005 , G11C29/46 , G11C29/787 , G11C2029/0407 , H01L27/10805 , H01L2224/4826 , H01L2224/73215 , H01L2924/1305 , H01L2924/13091 , H01L2924/00
Abstract: PROBLEM TO BE SOLVED: To provide a means for supplying a proper operation voltage to a large semiconductor memory device. SOLUTION: A voltage regulator for the dynamic random access memory for supplying an output voltage in response to an external voltage is provided with an external voltage supply circuit for supplying an external voltage as an output voltage when the external voltage is equal to or less than a first set value for defining a power-up range, an active reference circuit for receiving the external voltage and generating a reference signal having a desired relation with the external voltage, a 1-unit gain amplifier for generating a reference voltage in response to the reference signal when the external voltage is equal to or more than the first set value, a power amplifier stage for amplifying a reference voltage by a factor larger than one unit to provide an output voltage when the external voltage supply circuit does not supply an external voltage as an output voltage, and a pull-up stage for pulling-up the reference voltage to follow the external voltage when the external voltage exceeds a second set value for defining a burn-in range. COPYRIGHT: (C)2006,JPO&NCIPI
Abstract translation: 要解决的问题：提供一种用于向大型半导体存储器件提供适当的操作电压的装置。 解决方案：用于提供响应于外部电压的输出电压的动态随机存取存储器的电压调节器提供有外部电压供应电路，用于当外部电压等于或等于或等于 小于用于定义上电范围的第一设定值，用于接收外部电压并产生具有与外部电压的期望关系的参考信号的有源参考电路;用于响应地产生参考电压的1单位增益放大器 当所述外部电压等于或大于所述第一设定值时，将所述参考信号提供给所述参考信号;功率放大器级，用于放大参考电压乘以大于一个单位的系数，以在所述外部电压供应电路不供应时提供输出电压 外部电压作为输出电压，以及用于提升参考电压的上拉级，以便在外部电压优于 ds定义一个老化范围的第二个设定值。 版权所有（C）2006，JPO＆NCIPI
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公开(公告)号：JP2006190472A
公开(公告)日：2006-07-20
申请号：JP2006065347
申请日：2006-03-10
Inventor： KEETH BRENT , BUNKER LAYNE G , DERNER SCOTT J , TAYLOR RONALD L , MULLIN JOHN S , BEFFA RAYMOND J , ROSS FRANK F , KINSMAN LARRY D
IPC: G11C11/401 , G11C5/02 , G11C5/06 , G11C11/407 , G11C11/4074 , G11C11/4076 , G11C11/409 , G11C11/4097 , G11C29/04 , G11C29/14 , H01L21/8242 , H01L27/108
CPC classification number: G11C5/063 , G11C5/025 , G11C5/145 , G11C5/147 , G11C11/401 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C11/4099 , G11C29/021 , G11C29/028 , G11C29/12 , G11C29/12005 , G11C29/46 , G11C29/787 , G11C2029/0407 , H01L27/10805 , H01L2224/4826 , H01L2224/73215 , H01L2924/1305 , H01L2924/13091 , H01L2924/00
Abstract: PROBLEM TO BE SOLVED: To realize a high density memory by an economical method. SOLUTION: The dynamic random access memory is a plurality of individual arrays of memory cells, the memory has a plurality of individual arrays forming a plurality of array blocks and a plurality of sense amplifiers, a plurality of memory cells has a plurality of peripheral apparatus writing and reading information, a logic generating a redundant signal controlling a plurality of peripheral apparatus, a power source, and a plurality of pads, only a first layer and a second layer of a metal conductor performs mutual connection between a plurality of memory cells, a plurality of peripheral apparatus, the logic, the power source, and the plurality of pads, the redundant signal is sent to a second metal layer through the sense amplifier. COPYRIGHT: (C)2006,JPO&NCIPI
Abstract translation: 要解决的问题：通过经济的方法实现高密度存储器。 解决方案：动态随机存取存储器是存储器单元的多个单独阵列，存储器具有形成多个阵列块的多个单独阵列和多个读出放大器，多个存储单元具有多个 外围设备写入和读取信息，产生控制多个外围设备的冗余信号的逻辑，电源和多个焊盘，仅金属导体的第一层和第二层执行多个存储器之间的相互连接 单元，多个外围设备，逻辑电路，电源和多个焊盘，冗余信号通过读出放大器发送到第二金属层。 版权所有（C）2006，JPO＆NCIPI
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