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公开(公告)号：MX172939B
公开(公告)日：1994-01-24
申请号：MX2356590
申请日：1990-12-03
Applicant: MOTOROLA INC
Inventor： WHITE RICHARD E , CHANG HUNGKUN J , NOLAN MICHAEL P , FREEBURG THOMAS A , KACKZMARCZYK JOHN M , BUCHHOLZ DALE R
Abstract: In this invention a hierarchical addressing technique is employed in a packet communications system to enhance flexibility in handling packet information. This method permits packet message data (Fig. 3) and certain packet control data (Fig. 3) to be stored in memory locations (32, 34) without having to be duplicated at a different memory location prior to transmission of the packet. This method is preferably employed in a ring configuration in which a series of packets have addressing mechanisms which points sequentially to each other to form a ring of packets.
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公开(公告)号：HU205511B
公开(公告)日：1992-04-28
申请号：HU802990
申请日：1990-12-03
Applicant: MOTOROLA INC
Inventor： FREEBURG THOMAS A , KACZMARCZYK JOHN M , NOLAN MICHAEL P , BUCHHOLZ DALE R , WHITE RICHARD E , CHANG HUNGKUN J
Abstract: In this invention a hierarchical addressing technique is employed in a packet communications system to enhance flexibility in handling packet information. This method permits packet message data (Fig. 3) and certain packet control data (Fig. 3) to be stored in memory locations (32, 34) without having to be duplicated at a different memory location prior to transmission of the packet. This method is preferably employed in a ring configuration in which a series of packets have addressing mechanisms which points sequentially to each other to form a ring of packets.
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公开(公告)号：HU906258D0
公开(公告)日：1991-03-28
申请号：HU625890
申请日：1990-09-28
Applicant: MOTOROLA INC
Inventor： WHITE RICHARD E , BUCHHOLZ DALE R , JOHANSON LISA B , FREEBURG THOMAS A
IPC: H04L12/64
Abstract: A network interface architecture for a packet/fast packet switch is described. This architecture provides for the combination of both voice and data in a single switch using a common packet structure. It allows for the dynamic allocation of bandwidth based on system loading. This includes not only bandwidth within the voice or data areas of the frame, but also between the voice and data portions. The network interface (105) provides a means (101) of passing all packets through the Network Interface (105) or allowing the packet devices to directly transfer packets between one another. The bandwidth allocation can easily be changed because the control and data memories are synchronized to one another. The architecture allows for the data packets and the control of bandwidth allocation to be controlled by a single switching device. It synchronizes the transfer of the data and the allocation of bus bandwidth. The control of the packet devices can be controlled at a very high bit rate such as 40 Mbps. It allows packet devices to directly transfer packets. It allows for easy re-allocation of bandwidth through the use of the NI Base Registers.
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公开(公告)号：ES2169728T3
公开(公告)日：2002-07-16
申请号：ES93925061
申请日：1993-10-26
Applicant: MOTOROLA INC
Inventor： BUCHHOLZ DALE R , DOSS WILLIAM K , ROBBINS KAREN E , YEDINAK MARK A , HAMILTON R LEE JR
Abstract: A method and apparatus for preserving the sequential relationship of a plurality of data packets 310 generated by separate source devices 14 and ordered as a data stream 300, despite transmission over radio channels which introduce ordering errors comprises method steps and apparatus structure for identifying at a first terminal, data packets from within the data stream as a function of source, generating data packet sequence information for identified data packets, storing values corresponding to data packet sequence numbers as a function of source and transmitting data packets, source device identity and packet sequence information to a second terminal having first terminal source device and data packet sequence information. Upon receipt of a first terminal transmission, the second terminal retrieves from second terminal memory, first terminal data packet sequence information and compares the stored data packet sequence information with received data packet sequence information. As a function of the comparison, received data packets are forwarded to an appropriate application for further processing when sequence information sequence numbers compare and stored in an order determined by the sequence information when the sequence numbers do not compare.
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公开(公告)号：BR9404437A
公开(公告)日：1999-06-15
申请号：BR9404437
申请日：1994-02-25
Applicant: MOTOROLA INC
Inventor： BUCHHOLZ DALE R , DOSS WILLIAM K , ROBBINS KAREN E , HAMILTON LEE R
Abstract: A packet transmission system (100) for reducing request traffic contention and the likelihood of resource misallocation includes a communications controller (110) and a plurality of remote requesting units (112) requesting packet transmission services. In response to receipt of a request (302), the controller (110) transmits a grant (306) to a requesting unit (112) when packet transmission resources (304 & 310) are available or a request acknowledgment (306) when packet transmission resources (304 & 310) are unavailable. Each remote unit (112) comprise apparatus structure and method steps for transmitting requests (302) to the controller (110) and starting a first timer having an interval (T) determined as a function of a number (Q) of outstanding requests (302). Upon receipt of an acknowledgement (306), the remote unit (112) starts a second timer having an interval (T1) longer than the interval (T). Upon expiration of either the first timer or the second timer, the remote unit (112) will then and only then transmit a duplicate request (302). By limiting the number of duplicate requests transmitted by a remote unit (112), the present invention operates to reduce request traffic contention and the likelihood of resource misallocation.
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Patent Agency Ranking
公开(公告)号：CA2038952C
公开(公告)日：1998-02-03
申请号：CA2038952
申请日：1990-08-23
Applicant: MOTOROLA INC
Inventor： BUCHHOLZ DALE R , WHITE RICHARD E , JOHANSON LISA B , FREEBURG THOMAS A
Abstract: An improved network interface architecture for a packet/fast packet switch is described. This network interface architecture provides for the combination of both voice and data in a single switch using a common packet structure. It allows for the dynamic allocation of bandwidth based on system loading. This includes not only bandwidth within the voice or data areas of the frame, but also between the voice and data portions. The network interface (NI) provides a means (the NI-Bus) of passing all packets through the Network interface or allowing the packet devices to directly transfer packets between one another. The bandwidth allocation can easily be changed because the control and data memories are synchronized to one another. The network interface architecture, according to the invention, allows for the data packets and the control of bandwidth allocation to be controlled by a single switching device. It synchronizes the transfer of the data and the allocation of bus bandwidth. The control of the packet devices can be controlled at a very high bit rate such as, for example, 40 Mbps. It also allows packet devices to directly transfer packets. It allows for easy re-allocation of bandwidth, through the use of the NI Base Registers.
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公开(公告)号：HK99597A
公开(公告)日：1997-08-08
申请号：HK99597
申请日：1997-06-26
Applicant: MOTOROLA INC
Inventor： WHITE RICHARD E , BUCHHOLZ DALE R , JOHANSON LISA B , FREEBURG THOMAS A
Abstract: A network interface architecture for a packet/fast packet switch is described. This architecture provides for the combination of both voice and data in a single switch using a common packet structure. It allows for the dynamic allocation of bandwidth based on system loading. This includes not only bandwidth within the voice or data areas of the frame, but also between the voice and data portions. The network interface (105) provides a means (101) of passing all packets through the Network Interface (105) or allowing the packet devices to directly transfer packets between one another. The bandwidth allocation can easily be changed because the control and data memories are synchronized to one another. The architecture allows for the data packets and the control of bandwidth allocation to be controlled by a single switching device. It synchronizes the transfer of the data and the allocation of bus bandwidth. The control of the packet devices can be controlled at a very high bit rate such as 40 Mbps. It allows packet devices to directly transfer packets. It allows for easy re-allocation of bandwidth through the use of the NI Base Registers.
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公开(公告)号：CA2098578C
公开(公告)日：1997-02-18
申请号：CA2098578
申请日：1991-10-16
Applicant: MOTOROLA INC
Inventor： CHANG HUNGKUN J , DOSS WILLIAM KEVIN , NOLAN MICHAEL P , BUCHHOLZ DALE R , FREEBURG THOMAS A , MCKOWN JOHN , WHITE RICHARD E
Abstract: An antenna selection technique is used in an RF communication system in which user modules (UM1-UM5) communicate with at least one node (N1-N2). The UM's (UM1-UM5) and nodes (N1,N2) each have multiple antennae. The combination of each UM and node antenna is evaluated at the UM. Based on at least signal quality, the UM (UM1-UM5) selects its antenna and the best node antenna for use. An alternate antenna is selected if a person is determined to be present in a predetermined area adjacent a UM (UM1-UM5) corresponding to a predetermined RF power level.
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公开(公告)号：DK0446335T3
公开(公告)日：1995-02-27
申请号：DK90915014
申请日：1990-08-23
Applicant: MOTOROLA INC
Inventor： WHITE RICHARD E , BUCHHOLZ DALE R , FREEBURG THOMAS A , JOHANSON LISA B
Abstract: A network interface architecture for a packet/fast packet switch is described. This architecture provides for the combination of both voice and data in a single switch using a common packet structure. It allows for the dynamic allocation of bandwidth based on system loading. This includes not only bandwidth within the voice or data areas of the frame, but also between the voice and data portions. The network interface (105) provides a means (101) of passing all packets through the Network Interface (105) or allowing the packet devices to directly transfer packets between one another. The bandwidth allocation can easily be changed because the control and data memories are synchronized to one another. The architecture allows for the data packets and the control of bandwidth allocation to be controlled by a single switching device. It synchronizes the transfer of the data and the allocation of bus bandwidth. The control of the packet devices can be controlled at a very high bit rate such as 40 Mbps. It allows packet devices to directly transfer packets. It allows for easy re-allocation of bandwidth through the use of the NI Base Registers.
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公开(公告)号：AT112908T
公开(公告)日：1994-10-15
申请号：AT90915014
申请日：1990-08-23
Applicant: MOTOROLA INC
Inventor： WHITE RICHARD E , BUCHHOLZ DALE R , JOHANSON LISA B , FREEBURG THOMAS A
Abstract: A network interface architecture for a packet/fast packet switch is described. This architecture provides for the combination of both voice and data in a single switch using a common packet structure. It allows for the dynamic allocation of bandwidth based on system loading. This includes not only bandwidth within the voice or data areas of the frame, but also between the voice and data portions. The network interface (105) provides a means (101) of passing all packets through the Network Interface (105) or allowing the packet devices to directly transfer packets between one another. The bandwidth allocation can easily be changed because the control and data memories are synchronized to one another. The architecture allows for the data packets and the control of bandwidth allocation to be controlled by a single switching device. It synchronizes the transfer of the data and the allocation of bus bandwidth. The control of the packet devices can be controlled at a very high bit rate such as 40 Mbps. It allows packet devices to directly transfer packets. It allows for easy re-allocation of bandwidth through the use of the NI Base Registers.
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