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    SELECTIVE CALL SIGNALING SYSTEM AND METHOD WITH COMBINED WIDE AREA PAGING AND HIGH DATA RATE TRANSMISSIONS VIA RADIO TELEPHONE TRANSCEIVERS.
    16.
    发明公开
    SELECTIVE CALL SIGNALING SYSTEM AND METHOD WITH COMBINED WIDE AREA PAGING AND HIGH DATA RATE TRANSMISSIONS VIA RADIO TELEPHONE TRANSCEIVERS. 失效
    系统信令选择性的声誉和大跨度组合工艺为人们搜索，并提出无线电话发送者和接收者率高的数据传输。

    公开(公告)号：EP0671084A4

    公开(公告)日：1999-04-21

    申请号：EP94901673

    申请日：1993-11-23

    Applicant: MOTOROLA INC

    Inventor： DAVIS WALTER LEE

    IPC: H04B5/00 ,  H04W84/02 ,  H04B7/26

    CPC classification number: H04W84/022

    Abstract: A cooperative paging system (10) and radio telephone system (15) combine to provide conventional delivery of short paging messages to a combination pager/radio telephone (40) via a first communication path, while a radio telephone link operating at a higher data rate is used to deliver large data messages to the pager/radio telephone (40). The radio telephone link is formed by a transceiver section (205) of the pager/radio telephone (40) coupling to a radio telephone base station (50, 52) and calling up a paging terminal (32) of the paging system (10). The paging terminal (32) retrieves the large data messages from a temporary message memory (42) to deliver to the pager/radio telephone (40).

    VERY LOW BIT RATE VOICE MESSAGING SYSTEM USING ASYMMETRIC VOICE COMPRESSION PROCESSING
    17.
    发明公开
    VERY LOW BIT RATE VOICE MESSAGING SYSTEM USING ASYMMETRIC VOICE COMPRESSION PROCESSING 失效
    不对称语音压缩和非常低比特率工作相关的新闻语言体系USED

    公开(公告)号：EP0792502A4

    公开(公告)日：1998-12-23

    申请号：EP96923669

    申请日：1996-06-28

    Applicant: MOTOROLA INC

    Inventor： DAVIS WALTER LEE ,  HUANG JIAN-CHENG ,  JASINSKI LEON

    IPC: G10L19/00 ,  G10L19/02 ,  G10L19/04 ,  H03M7/30 ,  H04B14/04 ,  H04Q7/10 ,  H04Q7/16 ,  G10L3/02 ,  G10L9/00

    CPC classification number: G10L19/0212 ,  G10L25/27

    Abstract: An apparatus and method for processing a voice message to provide low bit rate speech transmission processes the voice message to generate speech parameters which are arranged into a two dimensional parameter matrix (502) including a sequence of parameter frames. The two dimensional parameter matrix (502) is transformed using a predetermined two dimensional matrix transformation function (414) to obtain a two dimensional transform matrix (506). Distance values representing distances between templates of a set of predetermined templates and the two dimensional transform matrix (506) are then derived. The distance values derived are identified by indexes identifying the templates of the set of predetermined templates. The distance values derived are compared, and an index corresponding to a template of the set of predetermined templates having a shortest distance is selected and then transmitted.

    PROGRAMMABLE READ ONLY MEMORY ADAPTIVE ROW DRIVER CIRCUIT AND OUTPUT CIRCUIT.
    18.
    发明公开
    PROGRAMMABLE READ ONLY MEMORY ADAPTIVE ROW DRIVER CIRCUIT AND OUTPUT CIRCUIT. 失效
    适应强大的线驱动电路和输出电路可编程只读存储器。

    公开(公告)号：EP0229081A4

    公开(公告)日：1990-03-22

    申请号：EP86903104

    申请日：1986-05-09

    Applicant: MOTOROLA INC

    Inventor： DAVIS WALTER LEE

    IPC: G11C17/06 ,  G11C17/18 ,  G11C7/00 ,  G11C8/00

    CPC classification number: G11C17/06 ,  G11C17/18

    Abstract: An I L programmable read only memory (26) operates in the read mode at very low power levels and at voltages down to 1 Volt. Switching between modes is accomplished merely by changing the voltage on the B+ terminal; 1-3 Volts for the read mode and 9-12 Volts for the program mode. The memory includes a row driver circuit (e.g. 40) to sink current from a row (e.g. 60) of memory elements when selectively activated. The row driver circuit has two current sinking capabilities, a low current capability for the read mode and a high current capability for the program mode. The memory also includes an output circuit (e.g. 80) that has a selectable dual non-inverting input differential amplifier (424-440) with each non-inverting input connected to a different column (e.g. 340) of memory elements. To program the memory elements, the output circuit includes two selectable programming current sources (402-410, 412-420) which self extinguish as soon as the memory element being programmed changes from its unprogrammed to its programmed state.

    RECEIVER HAVING A SELF BIASING DIRECT COUPLED DATA LIMITER.
    19.
    发明公开
    RECEIVER HAVING A SELF BIASING DIRECT COUPLED DATA LIMITER. 失效
    与SELBSTVORGESPANNTEM电耦合数据限幅器的接收器。

    公开(公告)号：EP0205460A1

    公开(公告)日：1986-12-30

    申请号：EP85905466

    申请日：1985-10-16

    Applicant: MOTOROLA INC

    Inventor： DAVIS WALTER LEE ,  PRIETO YOLANDA ,  SMOOT GEORGE WOODROW

    IPC: H04B1/16 ,  H04L25/06 ,  H04L27/14

    CPC classification number: H04L25/062

    Abstract: Un circuit d'interface est couplé entre le dernier étage d'un récepteur FSK (22) et un limiteur (40) pour fournir un signal de tension de polarisation au limiteur. Le récepteur comprend un circuit économiseur d'énergie (32) qui fournit de l'énergie de façon intermittente. Le circuit d'interface contient des détecteurs (42, 44) de maximum et de minimum qui dérivent et maintiennent des tensions correspondant aux valeurs maximale et minimale du signal discriminé du récepteur. Une moyenne de ces tensions maximale et minimale correspondantes est établie de façon prédéterminée afin de fournir la tension de polarisation au limiteur. Il devient ainsi possible de déterminer de façon précise et rapide un niveau approprié de tension de polarisation, et de la fournir au limiteur lorsque l'on fournit de l'énergie.

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