METHOD AND APPARATUS FOR ENCODING AND DECODING DATA
    11.
    发明申请
    METHOD AND APPARATUS FOR ENCODING AND DECODING DATA 审中-公开
    编码和解码数据的方法和装置

    公开(公告)号:WO2008067149A2

    公开(公告)日:2008-06-05

    申请号:PCT/US2007084390

    申请日:2007-11-12

    Abstract: A method and apparatus for selecting interleaver sizes for turbo codes is provided herein. During operation information block of size K is received. An interleaver size K is determined that is related to K, where K from a set of sizes; wherein the set of sizes comprise wherein a is an integer and f is a continuous integer between fmin and fmax, p takes integer values between pmin and pmax, a>1, pmax> pmin, pmin>1. The information block of size K is padded into an input block of size K using filler bits, if needed. Encoding is performed using the original input block and the interleaved input block to obtain a codeword block using a turbo encoder. The codeword block is transmitted through the channel.

    Abstract translation: 本文提供了一种用于选择turbo码的交织器大小的方法和装置。 在操作期间,接收大小为K的信息块。 确定与K相关的交织器尺寸K,其中来自一组尺寸的K; 其中所述尺寸集合包括其中a是整数,f是在f min和f max之间的连续整数,p是pmin和pmax之间的整数,a> 1,pmax> pmin,pmin> 1。 如果需要,使用填充位将尺寸K的信息块填充到大小为K的输入块中。 使用原始输入块和交错输入块执行编码,以使用turbo编码器来获得码字块。 码字块通过信道传输。

    12.
    发明专利
    未知

    公开(公告)号:BRPI0813136A2

    公开(公告)日:2014-12-23

    申请号:BRPI0813136

    申请日:2008-06-17

    Applicant: MOTOROLA INC

    Abstract: During operation of a transmitter a circular buffer is created where only column tops of the circular buffer are defined as a starting position for a redundancy version. Where the circular buffer is in sequence format, all possible redundancy versions are positioned as a function of the column index of the starting position of the first redundancy version.

    MULTI-LAYER CYCLIC REDUNDANCY CHECK CODE IN WIRELESS COMMUNICATION SYSTEM

    公开(公告)号:CA2698533C

    公开(公告)日:2014-06-17

    申请号:CA2698533

    申请日:2008-09-10

    Applicant: MOTOROLA INC

    Abstract: A communication device is disclosed. The device is configured to generate a first block of first cyclic redundancy check (CRC) parity bits on a transport block wherein the first block of CRC parity bits is based on a first generator polynomial, to attach the first block of CRC parity bits to the transport block and to segment the transport block into multiple code blocks. The processor is also configured to generate a second block of CRC parity bits on each code block wherein the second block of CRC parity bits is based on a second generator polynomial that is different than the first generator polynomial. The first and second generator polynomials have a common degree. A second block of CRC parity bits is attached to each code block and the code blocks are concatenated after channel encoding.

    14.
    发明专利
    未知

    公开(公告)号:BRPI0721176A2

    公开(公告)日:2014-03-18

    申请号:BRPI0721176

    申请日:2007-11-12

    Applicant: MOTOROLA INC

    Abstract: Methods and apparatus for turbo encoding and turbo decoding are provided herein. During operation of the turbo encoder (101) or turbo decoder (304) the size of the turbo interleaver (201,401,402) is determined in dependence on the information block size and the appropriate interleaving parameters are selected. These parameters configure the turbo interleaver, which is a contention-free interleaver and which is based on either a quadratic permutation polynomial QPP interleaver or an almost regular permutation ARP interleaver. If the information block size does not match a supported interleaver size, then the information block is padded by means of filler bits insertion.

    18.
    发明专利
    未知

    公开(公告)号:BRPI0807977A2

    公开(公告)日:2014-06-10

    申请号:BRPI0807977

    申请日:2008-02-13

    Applicant: MOTOROLA INC

    Abstract: A method and apparatus for turbo encoding with a contention-free interleaver is provided herein. During operation an input block of size K′ is received. The original input block and the interleaved input block are encoded to obtain a codeword block, wherein the original input block is interleaved using an interleaver of size K′ and a permutation &pgr;(i)=(f1×i+f2×i2)mod K′, where 0≦̸i≦̸K′−1 is the sequential index of the symbol positions after interleaving, &pgr;(i) is the symbol index before interleaving corresponding to position i, K′ is the interleaver size in symbols, and f1 and f2 are the factors defining the interleaver. The values of K′, f1, f2 are taken from at least one row of a table. The codeword block is transmitted through the channel.

    METODO Y APARATO PARA CODIFICAR Y DECODIFICAR DATOS

    公开(公告)号:AR065503A1

    公开(公告)日:2009-06-10

    申请号:ARP080100815

    申请日:2008-02-27

    Applicant: MOTOROLA INC

    Abstract: Aquí se provee un método y aparato de turbo codificacion con un intercalador sin contencion. Durante la operacion, se recibe un bloque de entrada de tamano K. El bloque de entrada original y el bloque de entrada intercalado se codifican para obtenerun bloque de palabra codigo, donde el bloque de entrada original se intercala usando un intercalador de tamano K y una permutacion, donde 0 i K-1 es el índice secuencial de las posiciones de símbolo después del intercalado, (i) es el índice desímbolos antes del intercalado correspondiente a la posicion i, K es el tamano del intercalador de símbolos, y f1 y f2 son los factores que definen el intercalador. Los valores de K, f1, f2 se toman de por lo menos una fila de una tabla. El bloquede palabra codigo se transmite por el canal.

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