12.
    发明专利
    未知

    公开(公告)号:DE3014658A1

    公开(公告)日:1980-11-06

    申请号:DE3014658

    申请日:1980-04-16

    Applicant: MOTOROLA INC

    Abstract: An interface circuit is disclosed for receiving a ground-referenced A.C. signal for detecting transitions of the A.C. signal about ground potential. An input transistor is enabled when the A.C. signal voltage falls below ground potential by one base-emitter forward drop. The input transistor is disabled when the A.C. signal voltage rises above ground potential by one base-emitter forward drop. A feedback circuit and a bias circuit are coupled to the input transistor for switching the threshold levels of the input transistor. The interface circuit employs a hysteresis-type switching action for improving noise immunity while providing a symmetric output waveform. The circuit requires only a single power supply and is suitable for fabrication as a highly dense, monolithic integrated circuit. Also, the circuit provides a low input impedance to large positive and negative voltage transients.

    14.
    发明专利
    未知

    公开(公告)号:FR2603397B1

    公开(公告)日:1989-07-07

    申请号:FR8712168

    申请日:1987-09-01

    Applicant: MOTOROLA INC

    Abstract: A DC control loop is disclosed which is used in conjunction with a control circuit to precisely set the maximum control voltage produced by the control circuit for maximizing the gain of an attenuator controlled thereby. The attenuator includes a current mirror having an output for sourcing a DC current the magnitude of which is proportional to the gain of the attenuator and the control circuit includes a capacitor that is charged or discharged accordingly to vary the magnitude of the control voltage. The DC control loop includes a circuit for sinking the current supplied from the current mirror and a current of a predetermined magnitude, the circuit being coupled to the output of the current mirror and a transistor which is turned on when the magnitude of the current from the current mirror equals the magnitude of the current sank by the circuit to inhibit further charge or discharge of the capacitor whereby the gain of the attenuator is held at a predetermined maximum value.

    A CONTROL CIRCUIT HAVING A DIRECT CURRENT CONTROL LOOP FOR CONTROLLING THE GAIN OF AN ATTENUATOR

    公开(公告)号:GB2194694A

    公开(公告)日:1988-03-09

    申请号:GB8717706

    申请日:1987-07-27

    Applicant: MOTOROLA INC

    Abstract: A DC control loop is disclosed which is used in conjunction with a control circuit to precisely set the maximum control voltage produced by the control circuit for maximizing the gain of an attenuator controlled thereby. The attenuator includes a current mirror having an output for sourcing a DC current the magnitude of which is proportional to the gain of the attenuator and the control circuit includes a capacitor that is charged or discharged accordingly to vary the magnitude of the control voltage. The DC control loop includes a circuit for sinking the current supplied from the current mirror and a current of a predetermined magnitude, the circuit being coupled to the output of the current mirror and a transistor which is turned on when the magnitude of the current from the current mirror equals the magnitude of the current sank by the circuit to inhibit further charge or discharge of the capacitor whereby the gain of the attenuator is held at a predetermined maximum value.

    16.
    发明专利
    未知

    公开(公告)号:IT8148984D0

    公开(公告)日:1981-07-27

    申请号:IT4898481

    申请日:1981-07-27

    Applicant: MOTOROLA INC

    Abstract: A cascode circuit arrangement comprising an input current mirror circuit for providing an output current substantially equal to a supplied input current and an output circuit coupled in cascode to the output of the input current mirror and the output of the circuit. The output circuit comprises a pair of NPN transistors connected in a Darlington amplifier configuration which is supplied a constant bias potential as the input of the amplifier. The Darlington amplifier is coupled in cascode between the output of the current mirror and the output of the current source to buffer the same from variations in the output voltage supplied at the output. The output circuit includes a PNP lateral transistor the emitter of which is coupled between the interconnected emitter and base of said pair of transistors, the base is coupled to the bias potential and the collector to the output of the current mirror such that the reverse base current of the cascoded one of said pair of transistors is returned to the output of the current mirror to eliminate reverse base current error when the BVCEO of the cascoded transistor is exceeded.

    SPEAKERPHONE WITH FAST IDLE MODE
    17.
    发明专利

    公开(公告)号:GB2194868B

    公开(公告)日:1990-10-24

    申请号:GB8717272

    申请日:1987-07-22

    Applicant: MOTOROLA INC

    Abstract: A speakerphone circuit having fast sensitive switching between the receive mode and the transmit mode is disclosed which includes circuitry for providing four point sensing at the input and output of both the transmit and receive attenuators located in the transmit and receive signal paths thereof for controlling the gains of the attenuators in a complementary manner. A logic control circuit comprising a controller circuit provides an attenuator algorithm that first detects that voice signals are present in both signal paths then quickly causes the attenuators to be set to equal gains during a fast idle mode to then allow the stronger of the two signals to set the operating mode of the speakerphone.

    SPEAKERPHONE WITH FAST IDLE MODE
    18.
    发明专利

    公开(公告)号:GB2194868A

    公开(公告)日:1988-03-16

    申请号:GB8717272

    申请日:1987-07-22

    Applicant: MOTOROLA INC

    Abstract: A speakerphone circuit having fast sensitive switching between the receive mode and the transmit mode is disclosed which includes circuitry for providing four point sensing at the input and output of both the transmit and receive attenuators located in the transmit and receive signal paths thereof for controlling the gains of the attenuators in a complementary manner. A logic control circuit comprising a controller circuit provides an attenuator algorithm that first detects that voice signals are present in both signal paths then quickly causes the attenuators to be set to equal gains during a fast idle mode to then allow the stronger of the two signals to set the operating mode of the speakerphone.

    19.
    发明专利
    未知

    公开(公告)号:IT1154313B

    公开(公告)日:1987-01-21

    申请号:IT4901382

    申请日:1982-08-20

    Applicant: MOTOROLA INC

    Abstract: A relaxation oscillator which is suited for fabrication as a monolithic circuit and which uses a parallel resistive capacitive frequency determining network wherein a capacitor is charged and discharged between an upper and lower voltage level. As the capacitor is charged to a potential exceeding a first threshold voltage level supplied to a comparator switch, the operating state of the comparator is caused to switch. A current detecting circuit is included which detects a current that is proportional to the charging current supplied to the capacitor from a charge circuit. As the proportional current decreases in value below a predetermined level due to the capacitor being charged to the upper voltage level the current detecting circuit is disabled which actuates a control circuit for switching the threshold voltage applied to the comparator to a lower level. The actuated control circuit also disables the charge circuit such that the capacitor discharges to the lower voltage level at which time the comparator switches states to disable the control circuit whereby the threshold voltage level is switched to the first level. Thereafter, the charge circuit is enabled to enable the current detecting circuit and to charge the capacitor to the upper voltage level.

    20.
    发明专利
    未知

    公开(公告)号:IT1142954B

    公开(公告)日:1986-10-15

    申请号:IT4898481

    申请日:1981-07-27

    Applicant: MOTOROLA INC

    Abstract: A cascode circuit arrangement comprising an input current mirror circuit for providing an output current substantially equal to a supplied input current and an output circuit coupled in cascode to the output of the input current mirror and the output of the circuit. The output circuit comprises a pair of NPN transistors connected in a Darlington amplifier configuration which is supplied a constant bias potential as the input of the amplifier. The Darlington amplifier is coupled in cascode between the output of the current mirror and the output of the current source to buffer the same from variations in the output voltage supplied at the output. The output circuit includes a PNP lateral transistor the emitter of which is coupled between the interconnected emitter and base of said pair of transistors, the base is coupled to the bias potential and the collector to the output of the current mirror such that the reverse base current of the cascoded one of said pair of transistors is returned to the output of the current mirror to eliminate reverse base current error when the BVCEO of the cascoded transistor is exceeded.

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