公开(公告)号：EP0712553A1

公开(公告)日：1996-05-22

申请号：EP94924477.0

申请日：1994-07-20

Applicant: MOTOROLA, INC.

Inventor： LEE, Edward, K., B.

IPC: H04J13 ,  H04B1 ,  H04B7 ,  H04L7

CPC classification number: H04B1/7097 ,  H04L7/0062

Abstract: In an adaptive CDMA receiver (20), a DS-SS received signal and a reference signal are equalized by minimizing the error between them. The received signal includes a desired DS-SS communication signal comprising binary bits coded with spreading chip sequences. The received signal is sampled at a chip rate to produce sampled received signals which are correlated with each other. The received samples are de-correlated by employing an orthogonal transformation algorithm to provide de-correlated elements corresponding to the received samples. The equalization process is accelerated by minimizing the error based on the de-correlated elements.

公开(公告)号：EP0701753A1

公开(公告)日：1996-03-20

申请号：EP94921246.0

申请日：1994-06-03

Applicant: MOTOROLA, INC.

Inventor： LEE, Edward, K., B. ,  CADD, Jimmy ,  FULGHUM, Tracy, L. ,  BABAYI, Robert, S.

IPC: H04B1 ,  H04B7 ,  H04J13 ,  H04L7

CPC classification number: H04L7/04 ,  H04B1/7097 ,  H04J13/00 ,  H04L7/041 ,  H04L7/046

Abstract: In a CDMA communication system (100) capable of communicating between a receiver (20) and a transmitter (10) direct sequence spread spectrum communication signals (30), a system and method for synchronizing receiver bit timing and transmitter timing. Transmitter (10) transmits a training bit sequence (31) followed by a transmitter bit timing sequence (33). The receiver (20) adaptively determines a representation of a despreading chip sequence using a tapped delay line equalizer (400). Receiver bit timing offset is determined based on the representation of the despreading chip sequence and the transmitter bit timing sequence (33).